Shift registers and counters

Shift registers, ring/Johnson/LFSR counters, ripple and synchronous counters, MOD-N design and counter speed limits with worked numericals.

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Why it matters

Frequency counters, digital tachometers, timers and event counters in instrumentation are all counters; serial links such as SPI, sensor daisy-chains and LED drivers are built on shift registers. Knowing how fast a counter can run, how to make it count to any modulus and how bits move through a register is basic to designing or troubleshooting any digital instrument.

Key ideas

Registers and shift registers. A register is a group of flip-flops sharing a clock, storing one word. In a shift register each flip-flop's output feeds the next one's D input, so on every clock edge the stored word moves one place.

  • SISO (serial in, serial out): a digital delay line; data appears at the output n clocks later.
  • SIPO (serial in, parallel out): serial-to-parallel conversion, e.g. receiving SPI data.
  • PISO (parallel in, serial out): parallel-to-serial conversion, e.g. reading a parallel ADC word out over one wire.
  • PIPO: a plain storage register.
  • Bidirectional and universal registers (e.g. 74194) select shift left, shift right, parallel load or hold with mode inputs. A left shift of a binary number multiplies it by 2, a right shift divides by 2 (with the LSB lost).

Shift-register counters.

  • Ring counter: last output fed straight back to the first input, preset to a single 1. An n-bit ring has n states and needs no decoding (each state has one 1), but uses many flip-flops.
  • Johnson (twisted-ring) counter: the complement of the last output fed back. An n-bit Johnson counter has 2n states and each state can be decoded with one 2-input gate. Both have unused states and need a reset or self-correcting logic.
  • LFSR: XOR feedback from selected taps gives a maximal sequence of 2ⁿ − 1 states, used for pseudo-random test patterns and CRC.

Asynchronous (ripple) counters. Each flip-flop is a T flip-flop with T = 1; the first is clocked by the input, each later one by the previous output. Each stage divides the frequency by 2, so an n-bit ripple counter divides by 2ⁿ. The delays add: the last stage settles n·t_pd after the clock edge, and during the ripple the outputs pass through false intermediate states (decoding glitches). Down counting is obtained by clocking each stage from the previous Q′ (for negative-edge flip-flops) instead of Q.

Synchronous counters. All flip-flops share the clock; logic decides which ones toggle. For a binary up-counter with T flip-flops, Tᵢ = Q₀Q₁…Qᵢ₋₁ (a bit toggles when all lower bits are 1). All outputs change together after one t_pd, so the speed does not depend on the number of stages (beyond the AND-gate delay), and outputs are glitch-free. Arbitrary sequences are designed with state tables and flip-flop excitation tables (next topic).

MOD-N counters. A MOD-N counter has N states and divides the input frequency by N. It needs n = ⌈log₂N⌉ flip-flops. A ripple MOD-N counter can be made by decoding state N and using it to clear all flip-flops asynchronously (a decade counter clears on 1010). State N exists briefly (a few ns) and causes a glitch; a synchronous design avoids this by loading 0 at state N − 1. The 7490 is a ripple decade counter; the 74163 and 74193 are synchronous.

Applications. Frequency division, event counting, measuring frequency (count input pulses in a known gate time) or period (count reference clock pulses during one input period), timers and baud-rate generators.

Formulas

f_out = f_in / N

  • Output frequency of a MOD-N counter's last stage (Hz); for an n-bit binary counter N = 2ⁿ.

n = ⌈log₂ N⌉

  • Minimum number of flip-flops for N states.

f_max (ripple) = 1 / (n · t_pd)

  • t_pd: propagation delay of one flip-flop (s). Applies when the full count must settle (be decoded) within one clock period.

f_max (synchronous) = 1 / (t_pd + t_gate + t_su)

  • t_gate: delay of the toggle/next-state logic (s); t_su: setup time (s).

Ring counter states = n, Johnson counter states = 2n, Maximal LFSR states = 2ⁿ − 1

Worked examples

Example 1 (standard). Design a MOD-10 ripple counter and find its output frequency for a 1 MHz input.

  1. Flip-flops: n = ⌈log₂10⌉ = 4.
  2. Count 0000 to 1001; the count 1010 (decimal 10) must clear the counter. In 1010, Q₃ = 1 and Q₁ = 1, and no valid count 0–9 has both these bits set, so a 2-input NAND of Q₃ and Q₁ drives the active-low CLR of all four flip-flops.
  3. f_out = f_in / 10 = 1 MHz / 10 = 100 kHz.

Answer: 4 flip-flops, clear on Q₃·Q₁ via NAND; f_out = 100 kHz

Example 2 (GATE level). Each flip-flop has t_pd = 20 ns. (a) Find the maximum clock frequency of a 4-bit ripple counter if the count must be valid before the next clock. (b) For a 4-bit synchronous counter using the same flip-flops, AND gates with 10 ns delay and t_su = 5 ns, find f_max.

  1. (a) Worst-case settling = n·t_pd = 4 × 20 ns = 80 ns.
  2. f_max = 1 / 80 ns = 12.5 MHz.
  3. (b) T_min = t_pd + t_gate + t_su = 20 + 10 + 5 = 35 ns.
  4. f_max = 1 / 35 ns = 28.6 MHz.

Answer: (a) 12.5 MHz (b) 28.6 MHz

Example 3 (Johnson counter). A 4-bit Johnson counter (Q₀Q₁Q₂Q₃, Q₃′ fed back to Q₀) starts at 0000. List its states.

  1. Each clock: Q₀ ← Q₃′, Qᵢ ← Qᵢ₋₁.
  2. 0000 → 1000 → 1100 → 1110 → 1111 → 0111 → 0011 → 0001 → 0000.

Answer: 8 states (2 × 4), sequence repeats after 8 clocks

Common mistakes

  • Saying a ripple counter's frequency limit is 1/t_pd: that is true only if nobody reads the outputs; for valid decoded counts use n·t_pd.
  • Thinking a synchronous counter's f_max falls as n·t_pd (it does not; only the gate delay grows slightly).
  • Using 1001 (9) instead of 1010 (10) as the clear state for a ripple decade counter.
  • Confusing ring (n states) and Johnson (2n states) counters, or forgetting both have unused states.
  • Clocking a ripple down counter from Q instead of Q′ (for negative-edge flip-flops).

For GATE IN

Typical questions: find the sequence or modulus of a counter from its circuit (including counters cleared by a gate), output frequency after a chain of counters, number of states in ring, Johnson or LFSR counters, contents of a shift register after k clocks, and maximum clock frequency of ripple versus synchronous counters. Practise tracing states clock by clock and checking for unused or lock-out states.

Quick check

  1. A 3-bit ripple counter is clocked at 16 Hz. What is the MSB frequency?
  2. How many states does a 5-bit Johnson counter have?
  3. How many flip-flops are needed for a MOD-60 counter?
  4. Which shift register type converts serial data to parallel?
  5. Which counter type produces decoding glitches?

Answers: 1. 2 Hz 2. 10 3. 6 4. SIPO 5. Ripple (asynchronous) counter

See it move

All Instrumentation animations
Shift Register Visualization

Adjust the slider to see how data shifts through a Serial-In Serial-Out (SISO) shift register. Observe how the bits move with each clock pulse.

Equations used
  • f_out = f_in / 2^n — f_out: Output frequency (Hz), f_in: Input frequency (Hz), n: Number of flip-flops

Interview questions

All Digital Electronics and Microcontrollers interview questions

Try answering each one aloud before you open it.

  1. 1.What is a shift register and how does it work?Concept

    A shift register is a type of sequential logic circuit mainly used for storage or transfer of data. It consists of a series of flip-flops connected in a chain, where the output of one flip-flop becomes the input of the next. Data is shifted in or out of the register one bit at a time, either to the left or right, depending on the design. Shift registers can be used for data manipulation, data storage, and data transfer in digital circuits.

  2. 2.Explain the difference between a synchronous and an asynchronous counter.Concept

    A synchronous counter is a type of counter where all the flip-flops are driven by a common clock signal, ensuring that all the flip-flops change state simultaneously. In contrast, an asynchronous counter, also known as a ripple counter, has flip-flops that are not clocked simultaneously. Instead, the output of one flip-flop serves as the clock input for the next flip-flop, causing a ripple effect. Synchronous counters are generally faster and more reliable than asynchronous counters due to the simultaneous clocking.

  3. 3.Why are shift registers used in digital communication systems?Application

    Shift registers are used in digital communication systems for serial-to-parallel and parallel-to-serial data conversion. They allow data to be transmitted over a single line, reducing the number of required connections and simplifying the design. This is particularly useful in long-distance communication where minimizing the number of wires is crucial. Additionally, shift registers can be used for temporary data storage and data manipulation, making them versatile components in communication systems.

  4. 4.What happens if the clock frequency of a synchronous counter is increased beyond its limit?Application

    If the clock frequency of a synchronous counter is increased beyond its limit, the counter may not function correctly. The flip-flops may not have enough time to settle into their new states before the next clock pulse arrives, leading to incorrect counting or glitches. This is due to the propagation delay inherent in the flip-flops and the logic gates used in the counter. To ensure reliable operation, the clock frequency should be kept within the specified limits of the counter's components.

  5. 5.How does a Johnson counter differ from a ring counter?Concept

    A Johnson counter, also known as a twisted ring counter, is a type of shift register where the inverted output of the last flip-flop is fed back to the input of the first flip-flop. This configuration allows the counter to go through a sequence of states that is twice the number of flip-flops. In contrast, a ring counter has a feedback loop from the last flip-flop to the first without inversion, resulting in a sequence of states equal to the number of flip-flops. Johnson counters are more efficient in terms of state utilization compared to ring counters.

  6. 6.Calculate the maximum clock frequency of a 4-bit counter whose flip-flops have a propagation delay of 10 ns, for a ripple design and for a synchronous design.Numerical

    In a ripple counter the delays add, so the count is valid only n·t_pd = 4 × 10 ns = 40 ns after the edge, giving f_max = 1/40 ns = 25 MHz if the outputs must be read every cycle. In a synchronous counter all flip-flops switch together, so the limit is t_pd + gate delay + setup time; ignoring the gate and setup times it is 1/10 ns = 100 MHz, independent of the number of bits. That speed advantage is the main reason synchronous counters are preferred.

  7. 7.What is the purpose of using a counter in a digital circuit?Application

    Counters are used in digital circuits to count events, generate timing sequences, and divide frequencies. They can be used to keep track of the number of occurrences of a particular event, such as clock pulses, and are essential in applications like digital clocks, frequency counters, and event counters. Counters can also be used to create time delays and generate specific timing sequences required for various digital operations.

  8. 8.Explain how a 4-bit shift register can be used to implement a simple digital delay line.Application

    A 4-bit shift register can be used as a digital delay line by shifting data through the register at each clock pulse. The input data is delayed by a number of clock cycles equal to the number of stages in the shift register. For a 4-bit shift register, the data is delayed by four clock cycles. This setup can be used in applications where a specific time delay is required, such as in signal processing or data synchronization tasks.

  9. 9.What are the advantages of using a synchronous counter over an asynchronous counter?Application

    Synchronous counters have several advantages over asynchronous counters. They offer faster operation because all flip-flops are triggered simultaneously by a common clock signal, reducing the propagation delay. This simultaneous triggering also minimizes the risk of glitches and errors, making synchronous counters more reliable. Additionally, synchronous counters are easier to design for complex counting sequences and can be easily expanded by adding more flip-flops.

  10. 10.Determine the number of states in a 3-bit Johnson counter.Numerical

    A 3-bit Johnson counter has a sequence of states that is twice the number of flip-flops. Therefore, for a 3-bit Johnson counter, the number of states is 2 * 3 = 6. This means the counter will go through six unique states before repeating the sequence.

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