Sample-and-hold circuits

Sample-and-hold circuits: operation, acquisition time, aperture uncertainty, droop, hold step and why an S/H is needed before an ADC, with numericals.

Drafted with Aria, reviewed by the AiCanCode.org team. Spotted an error? Use Give Feedback at the bottom of the page.

Why it matters

An ADC needs a steady input for the whole of its conversion time. A successive-approximation ADC that takes 10 µs cannot digitise even a few-hertz full-scale sine to 12-bit accuracy unless something freezes the input first. The sample-and-hold (S/H) circuit does that, and its imperfections (acquisition time, aperture uncertainty, droop and hold step) often set the real accuracy of a data-acquisition channel.

Key ideas

Basic circuit. An input buffer (op-amp voltage follower) drives a hold capacitor C_H through an analog switch (usually a MOSFET); an output follower with very high input impedance reads the capacitor without discharging it.

  • Sample (track) mode: switch closed, the capacitor voltage follows the input. Strictly this is a track-and-hold; a true sample-and-hold takes only a brief sample.
  • Hold mode: switch open, the capacitor keeps the voltage it had at the moment of opening, and the output stays constant (ideally) while the ADC converts. Feedback versions place the capacitor inside an integrator or close the loop around both amplifiers to remove offset errors. Monolithic examples are the LF398 with an external capacitor, and S/H stages built into most microcontroller ADCs.

Specifications.

  • Acquisition time t_acq: time after the sample command for the capacitor to charge to within a stated error band (e.g. ½ LSB) of the input, for a full-scale step. With switch resistance R_on and source resistance it is set by the RC time constant and the op-amp slew rate.
  • Aperture time (aperture delay) t_ap: delay between the hold command and the switch actually opening. A fixed delay can be compensated by advancing the command.
  • Aperture uncertainty (jitter) Δt_a: the random variation of the aperture delay. It cannot be compensated and causes a voltage error equal to the input slope times Δt_a.
  • Droop rate: in hold, leakage currents (switch, capacitor, amplifier bias) slowly charge or discharge C_H: dV/dt = I_L / C_H.
  • Hold step (pedestal): when the switch opens, the charge injected by the MOSFET gate, Q_inj, shifts the held voltage by Q_inj / C_H.
  • Feedthrough: a fraction of the input appears at the output in hold through the switch capacitance.
  • Settling time: time for the output to settle after entering hold.

The capacitor trade-off. A large C_H lowers droop and hold step but lengthens acquisition time and needs more drive current. A small C_H is fast but droops and suffers from charge injection. Use low-leakage, low-dielectric-absorption capacitors (polystyrene, polypropylene, C0G ceramic), not electrolytics.

Why it is needed. Without an S/H the input must change by less than about ½ LSB during the whole conversion time t_c. For a sine of peak V_p, the maximum slope is 2πf·V_p, which gives very low allowable frequencies. With an S/H, the relevant time becomes the aperture uncertainty (nanoseconds), so the usable frequency rises by orders of magnitude. The S/H does not remove the need for an anti-aliasing filter: the sampling rate must still exceed twice the highest signal frequency (Nyquist).

Connection to other topics. Op-amp buffers come from analog electronics; S/H is the front end of SAR and other ADCs and of multi-channel data-acquisition systems, where several S/Hs can freeze all channels at the same instant (simultaneous sampling).

Formulas

dV/dt (droop) = I_L / C_H

  • I_L: total leakage current (A); C_H: hold capacitance (F); result in V/s.

ΔV_droop = (I_L / C_H) · t_hold

  • t_hold: hold duration (s).

ΔV_ped = Q_inj / C_H

  • Hold step from charge injection Q_inj (C).

V_err (aperture) = (dV_in/dt)max · Δt_a = 2π·f·V_p·Δt_a

  • For a sine of peak V_p (V) and frequency f (Hz); Δt_a: aperture uncertainty (s). The same formula with t_c in place of Δt_a applies to an ADC without S/H.

f_max = (½ LSB) / (2π · V_p · Δt), with LSB = V_FS / 2ⁿ

  • Highest full-scale sine frequency for ½ LSB error; V_FS = 2V_p for a bipolar range covering the full sine.

t_acq ≈ R·C_H · ln(2ⁿ⁺¹)

  • Time for an RC charge to settle within ½ LSB of an n-bit full-scale step; R: total series resistance (Ω). Ignores slew-rate limits.

Worked examples

Example 1 (standard). A hold capacitor of 1 nF has a total leakage current of 10 nA. A 12-bit ADC with 10 V full scale needs 20 µs to convert. Find the droop rate and the droop during one conversion, and compare with ½ LSB.

  1. Droop rate = I_L / C_H = 10 × 10⁻⁹ A / 1 × 10⁻⁹ F = 10 V/s (= 10 mV/ms).
  2. ΔV = 10 V/s × 20 × 10⁻⁶ s = 0.2 mV.
  3. LSB = 10 V / 4096 = 2.44 mV; ½ LSB = 1.22 mV.
  4. 0.2 mV < 1.22 mV, so droop is acceptable.

Answer: 10 V/s; 0.2 mV per conversion, well under ½ LSB

Example 2 (GATE level). A 12-bit ADC with a ±5 V range (V_FS = 10 V) digitises a full-scale sine (V_p = 5 V). Find the highest frequency for an error under ½ LSB (a) with an S/H of aperture uncertainty 1 ns, (b) without an S/H, the ADC taking 10 µs to convert.

  1. ½ LSB = 10 V / 4096 / 2 = 1.22 mV.
  2. f_max = (½ LSB) / (2π·V_p·Δt).
  3. (a) f_max = 1.22 × 10⁻³ / (2π × 5 × 1 × 10⁻⁹) = 38.9 kHz.
  4. (b) f_max = 1.22 × 10⁻³ / (2π × 5 × 10 × 10⁻⁶) = 3.89 Hz.

Answer: (a) about 38.9 kHz (b) about 3.9 Hz: the S/H raises the usable bandwidth 10 000 times

Example 3 (acquisition time). The switch and source resistance total 100 Ω and C_H = 1 nF. Estimate the acquisition time to settle within ½ LSB for a 12-bit converter.

  1. τ = R·C_H = 100 Ω × 1 nF = 100 ns.
  2. t_acq ≈ τ·ln(2¹³) = 100 ns × 9.01 = 0.90 µs.

Answer: about 0.9 µs (about 9 time constants)

Common mistakes

  • Writing droop as I·t/C but mixing nA, nF and ms, which gives answers 1000 times off. Convert everything to A, F and s.
  • Confusing aperture delay (fixed, can be compensated) with aperture uncertainty (random, cannot).
  • Thinking an S/H removes aliasing: it only freezes the input; the anti-aliasing filter and Nyquist rate are still needed.
  • Choosing a large capacitor for low droop without checking the acquisition time.
  • Using peak-to-peak voltage in the slope formula 2πfV_p.

For GATE IN

Expect numericals on droop (I/C), hold-step from charge injection, maximum signal frequency for a given aperture time or conversion time and resolution, and acquisition time from an RC; plus conceptual questions on why an S/H is needed before an ADC and on the capacitor trade-off. Practise the ½ LSB criterion carefully, stating whether V_FS is peak or peak-to-peak.

Quick check

  1. C_H = 10 nF, I_L = 1 nA. What is the droop over 1 ms?
  2. Which S/H error cannot be compensated by timing adjustment?
  3. A switch injects 1 pC into a 1 nF hold capacitor. What is the hold step?
  4. Does a bigger hold capacitor shorten or lengthen the acquisition time?

Answers: 1. 0.1 mV 2. Aperture uncertainty (jitter) 3. 1 mV 4. Lengthen

Interview questions

All Digital Electronics and Microcontrollers interview questions

Try answering each one aloud before you open it.

  1. 1.What is a sample-and-hold circuit, and what is its primary function?Concept

    A sample-and-hold circuit is an electronic device that samples an analog signal at a specific moment in time and holds onto its value for a certain period. Its primary function is to capture and maintain the voltage level of an analog signal so that it can be processed or converted to a digital signal without distortion or loss of information.

  2. 2.Explain the working principle of a sample-and-hold circuit.Concept

    A sample-and-hold circuit typically consists of a switch, a capacitor, and an operational amplifier. When the switch is closed, the capacitor charges to the voltage level of the input signal. Once the switch is opened, the capacitor holds this voltage level, maintaining it until the next sampling period. The operational amplifier buffers the output to prevent the capacitor from discharging.

  3. 3.Why are sample-and-hold circuits used in analog-to-digital converters (ADCs)?Application

    Sample-and-hold circuits are used in ADCs to stabilize the input analog signal during the conversion process. This ensures that the ADC has a constant input voltage to work with, which is crucial for accurate digital representation. Without a sample-and-hold circuit, the input signal might change during conversion, leading to errors.

  4. 4.What happens if the hold time of a sample-and-hold circuit is too short?Application

    If the hold time is too short, the circuit may not maintain the sampled voltage long enough for the subsequent processing or conversion to occur. This can lead to inaccuracies in the output signal, as the ADC or other processing units may not have sufficient time to accurately read the held value.

  5. 5.Describe the role of the capacitor in a sample-and-hold circuit.Concept

    The capacitor in a sample-and-hold circuit is responsible for storing the sampled voltage level. When the switch is closed, the capacitor charges to the input signal's voltage. Once the switch opens, the capacitor holds this voltage, maintaining it until the next sampling period. The capacitor's ability to hold the charge is crucial for the circuit's function.

  6. 6.How does the choice of capacitor affect the performance of a sample-and-hold circuit?Application

    The choice of capacitor affects the circuit's performance in terms of speed and accuracy. A larger capacitor can hold the charge longer, which is beneficial for longer hold times, but it may slow down the circuit's response time. Conversely, a smaller capacitor allows for faster sampling but may not hold the charge as effectively, leading to potential voltage droop.

  7. 7.What is aperture time in the context of sample-and-hold circuits?Concept

    Aperture time (aperture delay) is the delay between the hold command and the instant the switch actually opens and the value is frozen. A fixed aperture delay only shifts the sampling instant and can be compensated by advancing the command. Its random variation, the aperture uncertainty or jitter, cannot be compensated and causes an error equal to the input slope times the jitter, 2πfV_p·Δt_a for a sine, which limits the highest signal frequency that can be sampled accurately.

  8. 8.Calculate the voltage droop of a sample-and-hold capacitor of 10 nF with a leakage current of 1 nA over a hold time of 1 ms.Numerical

    Droop is ΔV = I·t / C. ΔV = (1 × 10⁻⁹ A × 1 × 10⁻³ s) / (10 × 10⁻⁹ F) = 1 × 10⁻⁴ V = 0.1 mV. The droop rate is I/C = 0.1 V/s. For a 12-bit, 10 V ADC (½ LSB ≈ 1.2 mV) this is negligible over 1 ms.

  9. 9.What factors can lead to errors in a sample-and-hold circuit?Application

    In sample mode, an insufficient acquisition time (RC of switch resistance and hold capacitor, op-amp slew rate) leaves the capacitor short of the input. At the sample-to-hold transition, aperture jitter causes a slope-dependent error and charge injection from the MOSFET switch causes a hold step. In hold, leakage currents cause droop at I/C, and feedthrough through the switch capacitance lets some input reach the output. Amplifier offsets and capacitor dielectric absorption add further errors.

  10. 10.If a sample-and-hold circuit has a sampling frequency of 1 kHz, what is the maximum signal frequency it can accurately sample according to the Nyquist theorem?Numerical

    According to the Nyquist theorem, the maximum signal frequency that can be accurately sampled is half of the sampling frequency. Therefore, if the sampling frequency is 1 kHz, the maximum signal frequency that can be accurately sampled is 500 Hz.

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