Semiconductor memories

Why it matters

A data logger stores readings in RAM, keeps its calibration constants in EEPROM and runs its program from flash. Choosing the right memory, sizing it and wiring several chips into one address space are routine tasks in instrument design, and memory capacity and expansion questions appear in almost every GATE paper on digital systems.

Key ideas

Organisation. A memory chip is an array of 2ⁿ locations (words), each m bits wide, written 2ⁿ × m. n address lines select a location through an internal decoder; m data lines carry the word. Control pins: chip select (CS′ or CE′), output enable (OE′) and write enable (WE′), usually active-low. With CS′ HIGH the data pins are high-impedance, so many chips can share a bus.

Volatile memories (RAM).

• SRAM: each bit is a cross-coupled latch (six transistors). Holds data as long as power is on, needs no refresh, fast (a few ns to tens of ns), but large per bit and costly. Used for processor registers, caches and microcontroller data memory.
• DRAM: each bit is one transistor and one capacitor (1T1C). Dense and cheap, but the charge leaks away, so every row must be refreshed periodically (typically every 64 ms) and reading is destructive (the row is rewritten after each read). The address is multiplexed into a row address (strobed by RAS′) and a column address (CAS′) to halve the address pins. Used for main memory.

Non-volatile memories.

• Mask ROM: contents fixed at manufacture; cheapest in volume.
• PROM: one-time programmable by blowing fuses (or antifuses).
• EPROM: floating-gate cells programmed electrically and erased by UV light through a quartz window, whole chip at once.
• EEPROM: electrically erasable byte by byte, in circuit; slower writes (ms) and limited endurance (roughly 10⁵–10⁶ cycles). Used for calibration data and settings.
• Flash: a floating-gate memory erased electrically in blocks or sectors, giving much higher density than EEPROM. NOR flash allows random-access reads (code execution); NAND flash is denser, read in pages (SD cards, SSDs). Endurance typically 10³–10⁵ erase cycles per block.
• Newer: FRAM and MRAM give fast non-volatile writes with very high endurance.

Memory as logic. A ROM with n address inputs and m outputs implements any m functions of n variables (a lookup table): the address decoder generates all minterms and the programmed array ORs them. PLAs and PALs are related programmable arrays with only the needed product terms.

Timing. Access time is the delay from a valid address (or chip select) to valid data out. Cycle time is the minimum time between successive accesses; for DRAM it exceeds the access time because of precharge and restore.

Memory expansion.

• Word-width (bit) expansion: chips in parallel share address and control lines, each supplies part of the data word. For an m-bit word from k-bit chips, use m/k chips per bank.
• Word-count (depth) expansion: banks share data lines; extra high-order address lines go to a decoder whose outputs drive the chip selects, so only one bank is enabled at a time.
• Total chips = (required words / chip words) × (required width / chip width).

Formulas

Capacity = 2ⁿ × m bits

• n: address lines; m: data lines (bits per word). Divide by 8 for bytes; 1 K = 1024.

n = log₂(number of locations)

Chips needed = (W_req / W_chip) × (m_req / m_chip)

• W: number of words; m: word width.

Decoder inputs = log₂(number of banks)

t_row = T_refresh / N_rows

• Interval between row refreshes when refreshes are spread evenly (s).

Refresh overhead = N_rows · t_RC / T_refresh

• t_RC: time for one row refresh (s).

Worked examples

Example 1 (standard). A memory chip has 11 address lines and 8 data lines. Find its organisation and capacity.

1. Locations = 2¹¹ = 2048 = 2 K.
2. Organisation: 2K × 8.
3. Capacity = 2048 × 8 = 16 384 bits = 16 Kbit = 2 KB.

Answer: 2K × 8, 16 Kbit (2 KB)

Example 2 (GATE level). A 16K × 16 memory is to be built from 4K × 4 RAM chips. Find the number of chips, the total address lines, how they are used and the decoder size.

1. Chips per bank (width): 16 / 4 = 4.
2. Banks (depth): 16K / 4K = 4.
3. Total chips = 4 × 4 = 16.
4. Address lines for 16K words: log₂(16 384) = 14.
5. Each chip has 4K words, so the 12 low-order lines A₁₁–A₀ go to every chip.
6. The 2 high-order lines A₁₃–A₁₂ drive a 2-to-4 decoder; each decoder output selects one bank of 4 chips.

Answer: 16 chips, 14 address lines, 12 to all chips and 2 to a 2-to-4 decoder

Example 3 (DRAM refresh). A DRAM has 8192 rows that must all be refreshed every 64 ms; one row refresh takes 50 ns. Find the row refresh interval for distributed refresh and the fraction of time spent refreshing.

1. t_row = 64 ms / 8192 = 7.8125 µs.
2. Overhead = 8192 × 50 ns / 64 ms = 409.6 µs / 64 ms = 0.0064.

Answer: one row every 7.81 µs; 0.64 % of the time

Common mistakes

• Forgetting to divide by 8 for bytes, or using 1 K = 1000 instead of 1024.
• Counting data lines as part of the address (capacity is 2ⁿ × m, not 2ⁿ⁺ᵐ).
• Connecting high-order address lines to every chip and leaving the decoder short of inputs.
• Calling EEPROM and flash the same: flash erases in blocks, EEPROM by byte.
• Saying DRAM is "slow because of refresh": it is slower mainly because sensing a tiny capacitor charge takes time, and refresh steals only a small fraction of cycles.

For GATE IN

Expect capacity and address-line calculations, chip counts and decoder sizes for memory expansion, address ranges of a chip selected by a given decoder, ROM implementation of functions, and properties of SRAM, DRAM, EPROM, EEPROM and flash. Practise writing the address map (start and end addresses in hex) of each chip in an expanded system.

Quick check

1. Capacity in bytes of a memory with 12 address and 16 data lines?
2. How many 1K × 8 chips make an 8K × 16 memory?
3. Which memory needs refresh?
4. How many address lines does a 64 KB byte-wide memory need?

Answers: 1. 8192 bytes 2. 16 3. DRAM 4. 16