Latches and flip-flops

Latches and flip-flops: SR, D, JK and T behaviour, characteristic and excitation tables, race-around, setup/hold timing, metastability and flip-flop conversion.

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Why it matters

A combinational circuit forgets its inputs the moment they change; a latch or flip-flop remembers one bit. Every register, counter, state machine, ADC output latch and microcontroller peripheral is built from them. Their timing limits (setup time, hold time and clock-to-output delay) set the maximum clock frequency of any synchronous system, and violating them causes the intermittent faults that are hardest to debug.

Key ideas

Bistable storage. Two inverting gates with cross-coupled feedback have two stable states, Q = 1 or Q = 0, and stay in either indefinitely. Adding inputs to force the state gives a latch.

SR latch.

  • NOR version (active-high inputs): S = 1 sets Q = 1, R = 1 resets Q = 0, S = R = 0 holds. S = R = 1 forces both Q and Q′ to 0, so they are no longer complements; if both inputs then return to 0 together, the final state is unpredictable. This input is therefore forbidden.
  • NAND version (active-low inputs S′, R′): S′ = R′ = 1 holds; S′ = R′ = 0 is forbidden (both outputs go to 1).
  • Use: switch debouncing, where a changeover switch drives S and R.

Gated latches. An enable (clock) input C gates S and R. The gated D latch sets S = D, R = D′, which removes the forbidden state: while C = 1 the output follows D (the latch is transparent); when C = 0 it holds the last value. A latch is level-sensitive.

Flip-flops. A flip-flop changes state only at a clock edge (rising or falling), so the output can change at most once per clock period. Edge triggering is obtained with a master-slave pair of latches enabled on opposite clock levels or with a dedicated edge-triggered circuit.

  • D: Q⁺ = D. The basic storage element of registers.
  • JK: like SR, but J = K = 1 toggles the output. Q⁺ = JQ′ + K′Q.
  • T: toggles when T = 1, holds when T = 0. Q⁺ = T ⊕ Q. Basis of counters.
  • SR (clocked): Q⁺ = S + R′Q with SR = 0. Asynchronous preset (PR) and clear (CLR) inputs, usually active-low, force the output immediately regardless of the clock; they are used for power-on reset.

Race-around. In a level-triggered JK latch with J = K = 1, the output toggles, feeds back and toggles again for as long as the clock stays HIGH. It occurs when the clock pulse width exceeds the propagation delay of the latch. Cures: master-slave construction or true edge triggering.

Characteristic and excitation tables. The characteristic equation gives the next state from inputs and present state (analysis). The excitation table gives the inputs needed for a desired transition (design of counters and state machines). For a JK flip-flop: 0→0 needs J = 0, K = X; 0→1 needs J = 1, K = X; 1→0 needs J = X, K = 1; 1→1 needs J = X, K = 0.

Timing parameters.

  • Setup time t_su: D must be stable this long before the active edge.
  • Hold time t_h: D must stay stable this long after the edge.
  • Clock-to-Q delay t_pd (or t_cq): time from the edge to a valid output.
  • If setup or hold is violated the flip-flop can become metastable: its output hovers between levels for an unpredictable time before settling. Asynchronous inputs (push-buttons, sensor pulses from another clock domain) are brought in through a two-flip-flop synchroniser to make this very unlikely.

Converting flip-flops. Drive the available flip-flop's inputs with logic derived from its excitation table. Examples: D from JK: J = D, K = D′. T from JK: J = K = T. T from D: D = T ⊕ Q. JK from D: D = JQ′ + K′Q.

Formulas

Q⁺ = D (D flip-flop)

Q⁺ = J·Q′ + K′·Q (JK flip-flop)

Q⁺ = T ⊕ Q = T·Q′ + T′·Q (T flip-flop)

Q⁺ = S + R′·Q, with S·R = 0 (SR flip-flop)

T_clk(min) = t_pd(FF) + t_comb(max) + t_su and f_max = 1 / T_clk(min)

  • t_pd: clock-to-Q delay (s); t_comb(max): longest logic delay between flip-flops (s); t_su: setup time (s). With clock skew t_skew that delays the capturing flip-flop's clock, T_clk(min) reduces by t_skew; skew in the other direction adds to it.

t_pd(FF, min) + t_comb(min) ≥ t_h (hold condition, independent of clock frequency)

Race-around condition (level-triggered JK, J = K = 1): t_w > t_pd

  • t_w: clock pulse width (s).

Worked examples

Example 1 (standard). A negative-edge-triggered JK flip-flop starts with Q = 0. On five successive clock edges the inputs (J, K) are (1, 0), (1, 1), (1, 1), (0, 1), (0, 0). Find Q after each edge.

  1. Use Q⁺ = JQ′ + K′Q.
  2. Edge 1: J = 1, K = 0 → set → Q = 1.
  3. Edge 2: J = K = 1 → toggle → Q = 0.
  4. Edge 3: toggle → Q = 1.
  5. Edge 4: J = 0, K = 1 → reset → Q = 0.
  6. Edge 5: J = K = 0 → hold → Q = 0.

Answer: Q = 1, 0, 1, 0, 0

Example 2 (GATE level). In a synchronous circuit, each flip-flop has t_pd = 10 ns (clock to Q, maximum), t_su = 5 ns and t_h = 2 ns. The longest combinational path between two flip-flops is 25 ns and the shortest is 1 ns; the minimum clock-to-Q delay is 3 ns. Find the maximum clock frequency and check the hold condition.

  1. T_clk(min) = t_pd + t_comb(max) + t_su = 10 + 25 + 5 = 40 ns.
  2. f_max = 1 / 40 ns = 25 MHz.
  3. Hold: t_pd(min) + t_comb(min) = 3 + 1 = 4 ns ≥ t_h = 2 ns, so hold is met.

Answer: f_max = 25 MHz; hold satisfied with 2 ns to spare

Example 3 (conversion). Make a T flip-flop from a D flip-flop.

  1. T flip-flop: Q⁺ = T ⊕ Q. D flip-flop: Q⁺ = D.
  2. Equate: D = T ⊕ Q, i.e. feed D from an XOR of T and Q.

Answer: D = T ⊕ Q

Common mistakes

  • Calling a latch a flip-flop: a latch is transparent during the whole enable level, a flip-flop samples only at the edge.
  • Saying S = R = 1 in a NOR latch makes Q "undefined"; it actually forces Q = Q′ = 0, and the problem appears when both inputs are released.
  • Mixing up the JK characteristic equation (Q⁺ = JQ′ + K′Q, not JQ + K′Q′).
  • Adding setup time to the hold check or thinking a slower clock fixes a hold violation; it does not.
  • Forgetting that asynchronous preset/clear act immediately and override the clock.

For GATE IN

Questions trace flip-flop outputs through a sequence of clock edges, ask for the function realised when one flip-flop is converted to another, find the maximum clock frequency from setup, delay and logic times (sometimes with skew), and test understanding of race-around, latches versus flip-flops and asynchronous inputs. Practise writing state tables quickly and drawing timing diagrams edge by edge.

Quick check

  1. What happens to a NOR SR latch when S = R = 1?
  2. Write the characteristic equation of a T flip-flop.
  3. A JK flip-flop has J = K = 1 and Q = 0. What is Q after one clock edge?
  4. t_pd = 12 ns, t_comb = 30 ns, t_su = 8 ns. What is f_max?
  5. Which input must be connected to Q′ for a D flip-flop to divide the clock by 2?

Answers: 1. Q and Q′ are both forced to 0 (forbidden input) 2. Q⁺ = T ⊕ Q 3. 1 4. 20 MHz 5. D

Interview questions

All Digital Electronics and Microcontrollers interview questions

Try answering each one aloud before you open it.

  1. 1.What is the difference between a latch and a flip-flop?Concept

    A latch is level-sensitive: while its enable is active it is transparent and the output follows the input, and it holds when the enable goes inactive. A flip-flop is edge-triggered: it samples its input only at the rising or falling clock edge, so the output changes at most once per clock period. Flip-flops make synchronous design and timing analysis simple; latches are smaller and are used where transparency is useful, such as bus holding or time-borrowing designs.

  2. 2.What are setup time and hold time of a flip-flop?Concept

    Setup time is how long the data input must be stable before the active clock edge, and hold time is how long it must remain stable after the edge. If either is violated the flip-flop may capture the wrong value or go metastable. Setup violations are fixed by slowing the clock or shortening logic paths; hold violations do not depend on clock frequency and are fixed by adding delay to short paths.

  3. 3.What is metastability and how do you protect against it?Concept

    When a flip-flop's input changes inside its setup-hold window, the internal latch can balance near the switching threshold and its output may hover between 0 and 1 for an unpredictable time before resolving. It is unavoidable when sampling asynchronous signals such as push-buttons or signals from another clock domain. The standard protection is a synchroniser of two or more flip-flops in series, which gives the first stage a full clock period to resolve and makes the failure rate (MTBF) acceptably low.

  4. 4.What is the race-around condition in a JK flip-flop?Concept

    With J = K = 1 a level-triggered JK latch toggles; if the clock stays high longer than the propagation delay, the new output feeds back and makes it toggle again, so it oscillates and the final state is unknown. It is removed by a master-slave arrangement, where the master accepts input on one clock level and the slave updates on the other, or by edge triggering.

  5. 5.How do you convert a JK flip-flop into a T flip-flop and into a D flip-flop?Concept

    For a T flip-flop tie J and K together and drive them with T: J = K = T, so T = 1 toggles and T = 0 holds. For a D flip-flop drive J with D and K with D′ through an inverter, so the next state always equals D. Both follow from matching the JK excitation table to the target flip-flop's behaviour.

  6. 6.Why does a synchronous circuit have a maximum clock frequency?Concept

    Data launched by one flip-flop must pass through its clock-to-Q delay and the longest combinational path and still arrive one setup time before the next clock edge. So the clock period must be at least t_pd + t_comb(max) + t_su, and f_max is the reciprocal. For example 10 ns + 25 ns + 5 ns gives 40 ns, i.e. 25 MHz.

  7. 7.What are asynchronous preset and clear inputs used for?Concept

    Preset and clear (usually active-low) force a flip-flop's output to 1 or 0 immediately, without waiting for a clock edge, and override the synchronous inputs. They are used to put registers and state machines into a known state at power-on or on a reset button. They should not be driven by glitchy logic, because any glitch acts at once.

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