Data acquisition systems

Why it matters

A data acquisition system (DAS) is what turns a plant full of sensors into numbers on a screen or in a database. It ties together everything in this subject: signal conditioning, multiplexers, sample-and-hold, ADCs, microcontrollers, timers and serial links. Designing one means choosing resolution, sampling rate and channel architecture so that the stored data really represents the process.

Key ideas

Signal chain. Transducer → signal conditioning → anti-aliasing filter → analog multiplexer → sample-and-hold → ADC → processor (storage, display, control, communication).

• Transducer: converts the physical quantity (temperature, pressure, flow, strain) into an electrical signal, often millivolts or a resistance change.
• Signal conditioning: excitation (bridge supply, RTD current), amplification to use the ADC's full range, offset removal, linearisation, cold-junction compensation for thermocouples, isolation for safety, and differential (instrumentation-amplifier) inputs to reject common-mode noise.
• Anti-aliasing filter: a low-pass filter before sampling that removes components above half the sampling rate; it must come before the ADC, because once aliasing occurs it cannot be undone.
• Multiplexer: lets many channels share one ADC; its on-resistance, settling time and crosstalk add errors.
• Sample-and-hold: freezes the input during conversion.
• ADC: chosen for resolution and speed (SAR for general multichannel work, sigma-delta for slow high-resolution sensors, flash for very high speed).
• Processor: sets the sampling clock with a timer, reads the ADC (often by interrupt or DMA), scales readings to engineering units, stores or transmits them (UART, RS-485, Ethernet, 4–20 mA).

Single-ended versus differential inputs. Single-ended inputs measure against a common ground and suit high-level signals near the DAS. Differential inputs measure the difference of two wires and reject common-mode noise and ground-potential differences, which is essential for low-level signals such as thermocouples and strain-gauge bridges.

Multichannel architectures.

1. Multiplexer → one S/H → one ADC: cheapest; channels are sampled one after another, so there is a time skew between channels.
2. One S/H per channel → multiplexer → one ADC: all channels are held at the same instant (simultaneous sampling), needed when phase relations matter (e.g. voltage and current for power measurement).
3. One ADC per channel: highest throughput and simultaneous sampling; highest cost and power. Aggregate throughput = channels × per-channel sampling rate, and each conversion slot must cover multiplexer settling, S/H acquisition and ADC conversion.

Sampling rate. The Nyquist criterion requires f_s > 2f_max. Real filters are not ideal, so practical systems sample at 5–10 times f_max, or more for waveform display. A component at frequency f sampled at f_s appears at the alias frequency |f − k·f_s| (the nearest value in 0 to f_s/2). Slowly varying process variables (temperature, level) need only a few samples per second; vibration and power-quality signals need kHz to MHz.

Resolution and range. The number of bits follows from the required resolution relative to full scale: 2ⁿ ≥ span/resolution. Amplify the sensor signal so that its maximum just fills the ADC input range; otherwise the effective resolution is lost. Overall accuracy also depends on sensor accuracy, amplifier offset and drift, reference stability and noise, not just on the bit count.

Types of DAS. Analog versus digital; single-channel versus multichannel; centralised (all signals wired to one unit) versus distributed (remote I/O modules near the sensors communicating over a field bus), which reduces long analog wiring and noise pickup.

Formulas

f_s > 2·f_max (Nyquist; practical f_s ≈ 5–10·f_max)

f_alias = |f − k·f_s| (k chosen so the result lies in 0 to f_s/2)

f_aggregate = N_ch · f_s,ch and t_slot = 1 / f_aggregate ≥ t_mux + t_acq + t_conv

n ≥ log₂(span / required resolution)

G = V_ADC,FS / V_sensor,max (amplifier gain to fill the ADC range)

1 LSB referred to input = V_FS / (2ⁿ · G)

Worked examples

Example 1 (standard). An 8-channel DAS uses one multiplexer, one S/H and one ADC. Each channel must be sampled at 2 kHz. The multiplexer settles in 5 µs, S/H acquisition takes 10 µs and the ADC converts in 40 µs. Is the ADC fast enough?

1. Aggregate rate = 8 × 2 kHz = 16 kS/s.
2. Time slot per conversion = 1 / 16 000 = 62.5 µs.
3. Time needed = 5 + 10 + 40 = 55 µs.
4. 55 µs < 62.5 µs, so it works with 7.5 µs to spare.

Answer: Yes: 55 µs needed per channel against a 62.5 µs slot

Example 2 (GATE level). A temperature channel covers 0–500 °C and must resolve 0.1 °C. The sensor output (given) is 50 µV/°C, and the ADC has a 0–5 V input range. Find the minimum ADC bits, the amplifier gain and the resolution actually achieved.

1. Levels needed = 500 / 0.1 = 5000 → n ≥ log₂ 5000 = 12.3 → n = 13 (8192 levels).
2. Sensor maximum = 500 × 50 µV = 25 mV. Gain G = 5 V / 25 mV = 200.
3. LSB at the ADC = 5 V / 8192 = 0.610 mV; referred to the sensor = 0.610 mV / 200 = 3.05 µV.
4. In temperature: 3.05 µV / (50 µV/°C) = 0.061 °C, better than 0.1 °C.

Answer: 13 bits, gain 200, resolution ≈ 0.061 °C (a standard 16-bit ADC would usually be chosen in practice)

Example 3 (aliasing). A DAS samples at 1 kHz without an anti-aliasing filter. The input contains a 1.2 kHz interference component. At what frequency does it appear?

1. f_alias = |1200 − 1 × 1000| = 200 Hz, which lies within 0–500 Hz.

Answer: 200 Hz (indistinguishable from a genuine 200 Hz signal)

Common mistakes

• Putting the anti-aliasing filter after the ADC or relying on digital filtering to remove aliases.
• Sampling exactly at 2f_max and expecting a faithful waveform.
• Forgetting that a multiplexed system divides the ADC rate among the channels.
• Using the ADC bit count alone as the system accuracy, ignoring sensor, amplifier and reference errors.
• Connecting a low-level sensor single-ended over long cables, inviting ground-loop and mains pickup.

For GATE IN

Expect: minimum sampling rate and alias frequencies, ADC resolution and bits needed for a required measurement resolution, gain selection to fill the ADC range, throughput and timing of multiplexed systems, and the order and purpose of blocks in a DAS. Practise working out the resolution referred back to the physical quantity.

Quick check

1. Minimum sampling rate for a signal band-limited to 5 kHz?
2. How many levels does a 12-bit ADC have?
3. A 900 Hz tone sampled at 1 kHz aliases to what frequency?
4. Which architecture samples all channels at the same instant with one ADC?

Answers: 1. More than 10 kHz 2. 4096 3. 100 Hz 4. One S/H per channel followed by a multiplexer