Logic families: TTL and CMOS characteristics

TTL and CMOS voltage levels, noise margins, fan-out, propagation delay, CMOS dynamic power and output types, with worked numericals.

Drafted with Aria, reviewed by the AiCanCode.org team. Spotted an error? Use Give Feedback at the bottom of the page.

Why it matters

A logic gate is an analog circuit that is only treated as digital inside its specified voltage windows. When you connect a sensor interface, an old TTL board and a 3.3 V microcontroller together, the datasheet numbers of the logic family (input and output thresholds, current ratings, delay and power) decide whether the link works, how many inputs one output can drive and how hot the board runs.

Key ideas

Datasheet voltage levels. Every family specifies four voltages:

  • V_OH(min): the lowest voltage a valid HIGH output will give.
  • V_OL(max): the highest voltage a valid LOW output will give.
  • V_IH(min): the lowest input voltage guaranteed to be read as HIGH.
  • V_IL(max): the highest input voltage guaranteed to be read as LOW. Inputs between V_IL and V_IH are undefined. The gap between what an output guarantees and what an input needs is the noise margin.

TTL (transistor-transistor logic). Bipolar transistors, multi-emitter input, totem-pole output, single 5 V supply (4.75–5.25 V). Standard 74-series typical values: V_IL = 0.8 V, V_IH = 2.0 V, V_OL = 0.4 V, V_OH = 2.4 V; I_IL = −1.6 mA, I_IH = 40 µA, I_OL = 16 mA, I_OH = −400 µA; propagation delay about 10 ns and about 10 mW per gate. 74LS (low-power Schottky) uses Schottky clamps to stop saturation: about 9.5 ns and 2 mW per gate, I_OL = 8 mA, I_IL = −0.4 mA. A floating TTL input behaves as logic 1 but picks up noise; tie unused inputs properly. TTL inputs source current when LOW, so a LOW-level driver must sink it.

CMOS. A p-MOS pull-up network and an n-MOS pull-down network that are never both on in steady state, so static current is only leakage. Inputs draw almost no DC current (gate oxide), so fan-out is limited by input capacitance (speed) rather than by DC current. Thresholds scale with supply: V_IL ≈ 0.3·V_DD, V_IH ≈ 0.7·V_DD, and outputs swing nearly rail to rail. 4000B series runs from 3–18 V; 74HC from 2–6 V; 74HCT has TTL-compatible input thresholds. Unused CMOS inputs must never float: a floating gate can sit near V_DD/2, turning both transistors partly on and drawing large current. CMOS gates are sensitive to electrostatic discharge.

Power in CMOS. Power is drawn mainly while switching: each output transition charges or discharges the load capacitance, giving dynamic power proportional to C·V_DD²·f. It rises linearly with frequency, so at very high switching rates a CMOS gate can dissipate more than a TTL gate. A smaller short-circuit component flows during the transition when both networks conduct briefly, and leakage adds static power in deep-submicron processes.

Other families. ECL (emitter-coupled logic) keeps transistors out of saturation and is the fastest bipolar family, at the cost of high power and negative supply. RTL and DTL are historical. BiCMOS combines CMOS logic with bipolar output drivers.

Output types.

  • Totem-pole: active pull-up and pull-down; two such outputs must never be tied together.
  • Open-collector (TTL) / open-drain (CMOS): only a pull-down transistor; an external pull-up resistor is needed. Several outputs can share one line (wired-AND), as on I²C and interrupt lines.
  • Tri-state: HIGH, LOW or high-impedance, controlled by an enable; used on shared buses.

Figures of merit. Fan-out, noise margin, propagation delay t_pd = (t_PHL + t_PLH)/2, power per gate and the speed-power product (delay × power, an energy in joules).

Formulas

NM_H = V_OH(min) − V_IH(min) and NM_L = V_IL(max) − V_OL(max)

  • Noise margins in V; the usable margin is the smaller of the two.

Fan-out = min( I_OL / |I_IL| , |I_OH| / I_IH )

  • Currents in A from the datasheet; take the smaller ratio, rounded down. Applies to DC loading (TTL); for CMOS fan-out is limited by capacitance and delay.

t_pd = (t_PHL + t_PLH) / 2

  • Propagation delays in s.

SPP = t_pd × P_D

  • Speed-power product in J; P_D: average power per gate in W.

P_dyn = α · C_L · V_DD² · f

  • C_L: switched load capacitance (F); V_DD: supply (V); f: clock frequency (Hz); α: activity factor (fraction of clock cycles in which the node makes a full 0→1→0 cycle; α = 1 for a node toggling once per clock period as a square wave of frequency f). Energy drawn from the supply per 0→1 transition is C_L·V_DD², half of it lost in the pull-up and half stored then lost in the pull-down.

R_P(min) = (V_CC − V_OL(max)) / (I_OL(max) − n·|I_IL|)

  • Minimum pull-up resistance for an open-collector output driving n TTL loads, Ω.

Worked examples

Example 1 (standard). A standard 74-series TTL gate has V_OH = 2.4 V, V_OL = 0.4 V, V_IH = 2.0 V, V_IL = 0.8 V, I_OL = 16 mA, I_OH = −400 µA, I_IL = −1.6 mA, I_IH = 40 µA. Find the noise margins and fan-out.

  1. NM_H = V_OH − V_IH = 2.4 − 2.0 = 0.4 V.
  2. NM_L = V_IL − V_OL = 0.8 − 0.4 = 0.4 V.
  3. LOW-state fan-out = I_OL / |I_IL| = 16 mA / 1.6 mA = 10.
  4. HIGH-state fan-out = |I_OH| / I_IH = 400 µA / 40 µA = 10.
  5. Fan-out = min(10, 10) = 10.

Answer: NM_H = NM_L = 0.4 V; fan-out = 10

Example 2 (GATE level). A CMOS chip has 10⁶ gates, each with an effective switched capacitance of 20 fF. It runs at V_DD = 1.8 V and f = 500 MHz with activity factor α = 0.1. Estimate the dynamic power. What happens if V_DD is reduced to 1.2 V with everything else unchanged?

  1. P_dyn = α · N · C · V_DD² · f.
  2. = 0.1 × 10⁶ × 20 × 10⁻¹⁵ F × (1.8 V)² × 500 × 10⁶ Hz.
  3. = 0.1 × 10⁶ × 20 × 10⁻¹⁵ × 3.24 × 5 × 10⁸ = 3.24 W.
  4. Power scales as V_DD²: P' = 3.24 × (1.2/1.8)² = 3.24 × 0.444 = 1.44 W.

Answer: 3.24 W at 1.8 V; 1.44 W at 1.2 V

Example 3 (pull-up sizing). An open-collector 74-series output (I_OL = 16 mA, V_OL = 0.4 V, V_CC = 5 V) drives 4 standard TTL inputs (I_IL = −1.6 mA). Find the minimum pull-up resistance.

  1. R_P(min) = (V_CC − V_OL) / (I_OL − n·|I_IL|).
  2. = (5 − 0.4) / (16 mA − 4 × 1.6 mA) = 4.6 V / 9.6 mA = 479 Ω.

Answer: R_P ≥ about 479 Ω (choose the next standard value, 510 Ω)

Common mistakes

  • Computing noise margin as V_IH − V_IL (that is the undefined band, not a margin).
  • Taking only one fan-out ratio; both HIGH and LOW states must be checked, and the smaller wins.
  • Using P = V²/R for a CMOS gate: CMOS has no static resistive path, its power is dynamic, P = αCV²f.
  • Driving a 5 V CMOS input (V_IH = 3.5 V) directly from a TTL output (V_OH as low as 2.4 V): the HIGH level is not guaranteed. Use a pull-up or a 74HCT part.
  • Leaving CMOS inputs floating, or tying two totem-pole outputs together.

For GATE IN

Questions ask for noise margins or fan-out from given datasheet values, dynamic power of CMOS from C, V and f (often how power scales with V or f), identification of the logic function of a given transistor-level CMOS or TTL circuit, and comparisons of families by speed, power and noise immunity. Practise reading a CMOS pull-up/pull-down network: series n-MOS means AND in the pull-down, giving NAND at the output.

Quick check

  1. V_OH = 2.7 V, V_IH = 2.0 V: what is NM_H?
  2. Which family has the lowest static power?
  3. A CMOS node with C = 10 pF switches at f = 1 MHz from 5 V (α = 1). What is P_dyn?
  4. Why are open-collector outputs used on shared interrupt lines?
  5. In a CMOS gate, two n-MOS in series in the pull-down network implement which gate?

Answers: 1. 0.7 V 2. CMOS 3. 250 µW 4. Several outputs can be wire-ANDed on one line with a pull-up 5. NAND

Interview questions

All Digital Electronics and Microcontrollers interview questions

Try answering each one aloud before you open it.

  1. 1.What are TTL and CMOS logic families?Concept

    TTL (Transistor-Transistor Logic) and CMOS (Complementary Metal-Oxide-Semiconductor) are two types of digital logic families used in electronic circuits. TTL uses bipolar junction transistors to perform logic functions, while CMOS uses field-effect transistors. TTL is known for its speed and noise immunity, whereas CMOS is valued for its low power consumption and high density of logic gates.

  2. 2.Explain the main differences between TTL and CMOS logic families.Concept

    The main differences between TTL and CMOS are in power consumption, speed, and noise immunity. TTL circuits generally consume more power than CMOS circuits, especially when idle. CMOS circuits have higher input impedance and lower power consumption, making them suitable for battery-powered devices. TTL circuits are faster than CMOS in terms of switching speed, but CMOS has improved significantly over the years. Additionally, CMOS is more susceptible to static discharge compared to TTL.

  3. 3.Why is CMOS preferred over TTL in battery-powered devices?Application

    CMOS is preferred over TTL in battery-powered devices because it consumes significantly less power. CMOS circuits only draw power during the switching of states, whereas TTL circuits consume power continuously. This low power consumption makes CMOS ideal for devices where battery life is a critical factor.

  4. 4.What happens if a TTL output is connected to a 5 V CMOS input without any interfacing?Application

    The LOW level is fine (TTL V_OL ≤ 0.4 V is well below the CMOS V_IL of about 1.5 V), but the HIGH level is not guaranteed: TTL only promises V_OH ≥ 2.4 V while a 5 V CMOS input needs about 3.5 V. The input can sit in the undefined region, giving erratic logic and extra supply current because both CMOS transistors are partly on. The fix is a pull-up resistor to 5 V or a CMOS part with TTL-compatible inputs such as 74HCT.

  5. 5.How can you interface a TTL output to a CMOS input?Application

    To interface a TTL output to a CMOS input, a pull-up resistor can be used to ensure that the voltage levels are compatible. The pull-up resistor is connected between the TTL output and the power supply voltage of the CMOS logic. This helps in raising the TTL high-level output voltage to a level that is acceptable for the CMOS input.

  6. 6.What are the typical voltage levels for logic '0' and logic '1' in TTL and CMOS?Concept

    In TTL, a logic '0' is typically represented by a voltage between 0V and 0.8V, and a logic '1' is represented by a voltage between 2V and 5V. In CMOS, a logic '0' is usually between 0V and 1/3 of the supply voltage (Vdd), and a logic '1' is between 2/3 of Vdd and Vdd. These levels can vary slightly depending on the specific technology and supply voltage used.

  7. 7.Calculate the dynamic power dissipation of a CMOS inverter with a supply voltage of 5 V, a switching frequency of 1 MHz and a load capacitance of 10 pF.Numerical

    Dynamic power is P = C·V_DD²·f (activity factor 1, output making one full charge-discharge cycle per period). P = 10 × 10⁻¹² F × (5 V)² × 1 × 10⁶ Hz = 2.5 × 10⁻⁴ W = 250 µW. Doubling the frequency doubles it, and halving the supply cuts it to a quarter.

  8. 8.What is the significance of noise margin in TTL and CMOS logic families?Concept

    Noise margin is the measure of a circuit's ability to tolerate noise without misinterpreting the logic levels. In TTL and CMOS logic families, a higher noise margin indicates better noise immunity. TTL typically has a lower noise margin compared to CMOS, which makes CMOS more robust in noisy environments. The noise margin is crucial for ensuring reliable operation in digital circuits.

  9. 9.Explain why CMOS technology is more scalable than TTL.Application

    CMOS technology is more scalable than TTL because it allows for higher density of logic gates on a chip due to its lower power consumption and smaller transistor size. As technology advances, CMOS can be scaled down to smaller geometries, allowing for more complex and powerful integrated circuits. This scalability is a key reason why CMOS is the dominant technology in modern digital electronics.

  10. 10.Determine the fan-out of a TTL gate if the output current is 16 mA and the input current for each connected gate is 1.6 mA.Numerical

    The fan-out of a TTL gate is calculated by dividing the output current by the input current of each connected gate. Given that the output current is 16 mA and the input current is 1.6 mA, the fan-out is 16 mA / 1.6 mA = 10. This means the TTL gate can drive up to 10 similar gates.

Finished this topic? Mark it so your progress, study plan and readiness keep up.

Stuck on something here?

PreviousLogic minimisation with Karnaugh mapsNext Combinational circuits: adders, multiplexers, decoders