ADCs: flash, successive approximation and dual-slope

Quantisation and flash, counter-ramp, successive-approximation and dual-slope ADCs: operation, conversion time, comparator count and dual-slope relations with worked numericals.

Drafted with Aria, reviewed by the AiCanCode.org team. Spotted an error? Use Give Feedback at the bottom of the page.

Why it matters

Every digital instrument begins with an analog-to-digital converter: a digital multimeter uses a dual-slope ADC, a microcontroller reading a thermocouple amplifier uses a successive-approximation ADC, and a digital storage oscilloscope uses a flash ADC. Choosing the right architecture means trading speed, resolution, noise rejection, power and cost, and GATE regularly tests the numbers behind each one.

Key ideas

Quantisation. An n-bit ADC divides its full-scale range V_FS into 2ⁿ steps of size 1 LSB = V_FS/2ⁿ and outputs the integer code D for the step containing the input. The rounding introduces a quantisation error of up to ±½ LSB (for a mid-tread, rounding converter) or 0 to 1 LSB (for a truncating converter). For a full-scale sine the ideal signal-to-quantisation-noise ratio is about 6.02n + 1.76 dB. The input should be band-limited to below half the sampling rate (Nyquist) by an anti-aliasing filter and held constant during conversion by a sample-and-hold where the converter needs it.

Flash (parallel) ADC. A resistor string of 2ⁿ equal resistors divides V_ref into 2ⁿ − 1 threshold voltages, each fed to its own comparator. All comparators decide at once, giving a thermometer code (all comparators below the input read 1), which a priority encoder converts to binary.

  • Fastest type: one comparator delay plus encoder delay (nanoseconds).
  • Needs 2ⁿ − 1 comparators: 255 for 8 bits, 4095 for 12 bits, so power, area and input capacitance grow exponentially. Practical up to about 8 bits. Half-flash (sub-ranging) versions use two smaller flash stages.

Counter-ramp (tracking) ADC. A counter drives a DAC; the counter increments until the DAC output exceeds the input. Worst-case conversion time 2ⁿ clock periods, so it is slow and the conversion time depends on the input.

Successive-approximation (SAR) ADC. A SAR register, a DAC and one comparator perform a binary search. The MSB is set to 1 and the DAC output is compared with the input: if the DAC output is not more than the input the bit stays 1, otherwise it is cleared. Then the next bit is tried, and so on down to the LSB.

  • Conversion time is n clock periods (plus one or two for start and end), independent of the input.
  • Moderate speed (up to a few MS/s) at 8–18 bits, low power; the most common ADC in microcontrollers and data-acquisition systems.
  • The input must not change during conversion, so a sample-and-hold is essential; accuracy is limited by the internal DAC.

Dual-slope (integrating) ADC. An integrator first integrates the input V_in for a fixed time T₁ (a fixed count N₁ of clock pulses). Then the input is replaced by a reference of opposite polarity, −V_ref, and the integrator ramps back to zero while a counter measures the time T₂. Because the charge in equals the charge out, V_in·T₁ = V_ref·T₂, so N₂ = N₁·V_in/V_ref.

  • The result does not depend on R, C or the clock frequency (they cancel), only on V_ref: very accurate with cheap parts.
  • Integration averages noise; making T₁ an integer multiple of the mains period (20 ms for 50 Hz) rejects mains hum almost completely.
  • Slow: tens to hundreds of milliseconds per conversion. Used in digital panel meters and multimeters (3½ or 4½ digits).

Sigma-delta ADC (for comparison): oversampling with a 1-bit quantiser and digital filtering gives 16–24 bits at low bandwidth, used for weighing scales, thermocouples and audio.

Comparison. Speed: flash > SAR > dual-slope. Resolution and noise rejection: dual-slope and sigma-delta > SAR > flash. Comparators: flash 2ⁿ − 1, SAR and dual-slope one.

Formulas

1 LSB = V_FS / 2ⁿ and D = floor(V_in / LSB) (truncating)

  • V_FS: full-scale range (V); n: bits.

Quantisation error = ±½ LSB (rounding converter)

SQNR ≈ 6.02·n + 1.76 dB (full-scale sine)

Flash: comparators = 2ⁿ − 1, resistors = 2ⁿ

SAR: t_conv ≈ n · T_clk; counter ramp: t_conv(max) = 2ⁿ · T_clk

Dual slope: V_in · T₁ = V_ref · T₂ → N₂ = N₁ · V_in / V_ref

  • T₁: fixed integration time (s); T₂: de-integration time (s); N₁, N₂: counts at the same clock.

V_int(peak) = V_in · T₁ / (R·C)

  • Peak integrator output at the end of T₁ (V); must stay within the op-amp's output range.

Worked examples

Example 1 (standard: SAR trace). An 8-bit SAR ADC with V_FS = 10 V converts V_in = 6.3 V. A bit is kept if the DAC output is not more than V_in. Find the code.

  1. 1 LSB = 10 / 256 = 39.0625 mV.
  2. Try 10000000: DAC = 5.000 V ≤ 6.3 → keep.
  3. Try 11000000: 7.500 V > 6.3 → clear.
  4. Try 10100000: 6.250 V ≤ 6.3 → keep.
  5. Try 10110000: 6.875 V → clear. 10101000: 6.5625 V → clear. 10100100: 6.406 V → clear. 10100010: 6.328 V → clear.
  6. Try 10100001: 6.289 V ≤ 6.3 → keep.
  7. Result 10100001 = 161; 161 × 39.0625 mV = 6.289 V, error 10.9 mV (under 1 LSB).

Answer: 10100001₂ (161), reached in 8 clock cycles

Example 2 (GATE level: dual slope). A dual-slope ADC uses a 100 kHz clock. T₁ is chosen as 20 ms for 50 Hz rejection; V_ref = 2 V, R = 100 kΩ, C = 0.2 µF. For V_in = 1.25 V, find N₁, N₂, T₂, the peak integrator output and the maximum conversion time.

  1. N₁ = T₁ × f_clk = 0.020 s × 100 000 Hz = 2000 counts.
  2. N₂ = N₁·V_in/V_ref = 2000 × 1.25/2 = 1250 counts → T₂ = 1250/100 kHz = 12.5 ms.
  3. V_int(peak) = V_in·T₁/(RC) = 1.25 × 0.020 / (100 × 10³ × 0.2 × 10⁻⁶) = 0.025/0.02 = 1.25 V.
  4. Maximum T₂ occurs at V_in = V_ref: T₂ = T₁ = 20 ms, so t_conv(max) = 20 + 20 = 40 ms.

Answer: N₁ = 2000, N₂ = 1250, T₂ = 12.5 ms, peak 1.25 V, up to 40 ms per conversion

Example 3 (comparison). For 12 bits and a 1 MHz clock, compare SAR and counter-ramp conversion times, and give the flash comparator count.

  1. SAR: 12 × 1 µs = 12 µs.
  2. Counter ramp, worst case: 4096 × 1 µs = 4.096 ms.
  3. Flash: 2¹² − 1 = 4095 comparators.

Answer: 12 µs vs 4.096 ms; 4095 comparators

Common mistakes

  • Inverting the dual-slope relation: V_in = V_ref·T₂/T₁, and T₂ ≤ T₁ within range.
  • Thinking the dual-slope result depends on R, C or clock frequency; it does not (only the peak integrator voltage does).
  • Using 2ⁿ comparators for a flash ADC instead of 2ⁿ − 1.
  • Running a SAR ADC without a sample-and-hold on a changing input.
  • Mixing LSB = V_FS/2ⁿ with V_FS/(2ⁿ − 1); state which convention the question uses.

For GATE IN

Expect: SAR code or bit-by-bit trace for a given input, conversion times, number of comparators in flash and half-flash converters, dual-slope counts, times and integrator voltages, resolution and quantisation error, and which architecture suits a given application. Practise the SAR trace quickly and keep the dual-slope relation V_in·T₁ = V_ref·T₂ in mind.

Quick check

  1. How many comparators does a 6-bit flash ADC need?
  2. A 10-bit SAR ADC runs from a 2 MHz clock (one bit per clock). What is the conversion time?
  3. Dual-slope: N₁ = 1000, V_ref = 1 V, N₂ = 600. What is V_in?
  4. What is 1 LSB of a 10-bit ADC with V_FS = 5 V?

Answers: 1. 63 2. 5 µs 3. 0.6 V 4. 4.88 mV

Interview questions

All Digital Electronics and Microcontrollers interview questions

Try answering each one aloud before you open it.

  1. 1.What is an Analog-to-Digital Converter (ADC) and why is it important in digital electronics?Concept

    An Analog-to-Digital Converter (ADC) is a device that converts continuous analog signals into discrete digital numbers. It is important in digital electronics because most modern electronic devices process digital signals, so converting analog inputs (like sound, temperature, etc.) into digital form is essential for processing, storage, and transmission.

  2. 2.Explain how a flash ADC works.Concept

    A flash ADC, also known as a parallel ADC, uses a series of comparators to compare the input voltage with reference voltages. Each comparator outputs a binary signal, and the combination of these signals is decoded to produce the digital output. Flash ADCs are very fast because they convert the signal in a single step, but they require a large number of comparators, making them expensive and power-hungry for high-resolution applications.

  3. 3.Describe the working principle of a successive approximation ADC.Concept

    A successive approximation ADC uses a binary search algorithm to convert an analog signal to a digital one. It employs a digital-to-analog converter (DAC) and a comparator. The ADC starts with the most significant bit and sets it to 1, then compares the DAC output with the input signal. If the DAC output is less than the input, the bit remains 1; otherwise, it is set to 0. This process is repeated for each bit, resulting in a digital approximation of the analog input.

  4. 4.What is a dual-slope ADC and how does it differ from other types of ADCs?Concept

    A dual-slope ADC integrates the input for a fixed time T₁, then switches the integrator to a reference of opposite polarity and counts the time T₂ for the output to ramp back to zero. Since V_in·T₁ = V_ref·T₂, the count is proportional to V_in and independent of the integrator R, C and the clock frequency. Integration averages noise, and choosing T₁ as a multiple of the mains period rejects 50 Hz hum. It is far slower than flash or SAR converters (tens of ms) but very accurate and cheap, which is why digital multimeters use it.

  5. 5.Why is a flash ADC preferred in applications requiring high-speed data conversion?Application

    Flash ADCs are preferred in high-speed applications because they convert the analog signal to a digital output in a single step, using parallel comparators. This allows for very fast conversion times, making them ideal for applications like video processing and radar systems where speed is critical.

  6. 6.What would happen if a successive approximation ADC had a faulty comparator?Application

    If a successive approximation ADC had a faulty comparator, it could lead to incorrect bit decisions during the conversion process. This would result in inaccurate digital outputs, as the ADC relies on the comparator to determine whether each bit should be set to 1 or 0 based on the input signal.

  7. 7.In what scenarios would a dual-slope ADC be more advantageous than a flash ADC?Application

    A dual-slope ADC would be more advantageous in scenarios where accuracy and noise rejection are more important than speed, such as in digital multimeters and other precision measurement instruments. Its ability to average out noise over the integration period makes it suitable for environments with electrical noise.

  8. 8.Calculate the resolution of a 10-bit ADC with a reference voltage of 5V.Numerical

    The resolution of an ADC is the smallest change in voltage it can detect and is given by the formula: Resolution = V_ref / (2^n), where V_ref is the reference voltage and n is the number of bits. For a 10-bit ADC with a 5V reference, Resolution = 5V / (2^10) = 5V / 1024 = 0.00488V or 4.88mV.

  9. 9.A successive approximation ADC takes 8 clock cycles to convert an analog signal. If the clock frequency is 1 MHz, what is the conversion time?Numerical

    The conversion time for a successive approximation ADC is the number of clock cycles multiplied by the clock period. The clock period is the inverse of the clock frequency. For a 1 MHz clock, the period is 1/1,000,000 seconds = 1 microsecond. Therefore, the conversion time is 8 cycles × 1 microsecond/cycle = 8 microseconds.

  10. 10.How does the resolution of an ADC affect its performance in a digital system?Application

    The resolution of an ADC determines the smallest change in analog input that can be detected and represented in digital form. Higher resolution means more precise representation of the analog signal, which is crucial for applications requiring high accuracy. However, higher resolution also means more bits, which can increase the complexity and cost of the ADC.

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