Memory and I/O interfacing

Why it matters

A processor is useful only when it can reach memory and the outside world: EPROM holding the program, RAM holding readings, a keypad, a display, an ADC and relay drivers. Interfacing means giving each device its own address range, generating the right chip-select and read/write signals, and matching voltage, current and timing. Address-decoding questions are a GATE favourite because they test bus logic and binary arithmetic together.

Key ideas

System buses. The CPU drives the address bus and control lines (RD′, WR′, and in the 8085 IO/M′ and ALE); data flows on the bidirectional data bus. Every device connects to the data bus through tri-state outputs that are enabled only when that device is selected, so only one device drives the bus at a time.

Demultiplexing (8085). AD₀–AD₇ carry the low address byte in the first T-state and data afterwards. ALE pulses HIGH during the first T-state; an octal latch (74LS373) captures A₀–A₇ on ALE and holds them for the rest of the cycle.

Memory interfacing.

• A 2ᵏ-location chip uses the k low-order address lines A₀…A_(k−1) directly.
• The remaining high-order lines are decoded to generate the chip select (CS′). The 3-to-8 decoder 74LS138 is the usual choice: its select inputs take three address lines and its enables take further lines or IO/M′.
• RD′ drives the memory's OE′ and WR′ drives WE′ (combined with IO/M′ = 0 for memory cycles).

Full and partial decoding.

• Full (absolute) decoding: every high-order address line takes part, so each location has exactly one address.
• Partial (linear) decoding: some lines are ignored. Cheaper, but each location appears at 2ᵖ addresses (foldback or mirror images), where p is the number of unused lines, and those addresses cannot be used for anything else.

I/O interfacing.

• I/O-mapped (isolated) I/O: separate I/O space accessed by IN/OUT instructions; in the 8085 the port address is 8 bits, so up to 256 input and 256 output ports, with IO/M′ = 1. Only the accumulator can transfer data.
• Memory-mapped I/O: ports occupy memory addresses and are accessed with any memory instruction (all registers and addressing modes), at the cost of memory space. Microcontrollers (8051 external devices, ARM peripherals) use this.

Programmable peripheral interface 8255. Three 8-bit ports A, B and C plus a control register, selected by A₁A₀ (00 = A, 01 = B, 10 = C, 11 = control). In I/O mode (control-word D7 = 1) it is configured as: D6D5 = mode of group A (port A and upper C), D4 = port A direction (1 = input), D3 = upper port C direction, D2 = mode of group B, D1 = port B direction, D0 = lower port C direction. Mode 0 is simple I/O, mode 1 strobed (handshake) I/O, mode 2 bidirectional (port A only). With D7 = 0, the word sets or resets a single port C bit (BSR mode).

Typical devices.

• Switches: need pull-up resistors and debouncing (software delay of 10–20 ms or an SR latch).
• LEDs and seven-segment displays: series resistor R = (V_CC − V_F) / I_F; multiplexed displays share segment lines and enable one digit at a time.
• Matrix keypads: an r × c keypad needs r + c lines; the processor drives rows one at a time and reads the columns.
• ADC: start-of-conversion pulse, wait for end-of-conversion (polling or interrupt), then read with OE. DAC: write the code to a latched input.
• Loads beyond a pin's current rating: transistor, ULN2003 driver or opto-isolated relay.

Wait states. If a memory's access time exceeds the time the CPU allows, the READY line is pulled low to insert wait states (whole clock periods) until the data is valid.

Formulas

Address lines for a chip = log₂(locations)

Mirror images (partial decoding) = 2ᵖ

• p: number of high-order address lines not used in decoding.

Address range: start = (chip-select pattern on high lines, low lines all 0); end = start + size − 1

Keypad lines = r + c for r × c keys

R_LED = (V_CC − V_F) / I_F

• V_F: LED forward voltage (V); I_F: desired current (A).

Wait states = ⌈(t_access − t_allowed) / T_clk⌉

Worked examples

Example 1 (standard). An 8K × 8 EPROM in an 8085 system has its CS′ driven by output Y₂ of a 74LS138 whose select inputs C, B, A are A₁₅, A₁₄, A₁₃ (enables active for memory cycles). Find the address range.

1. 8K = 2¹³ locations → A₀–A₁₂ go to the chip.
2. Y₂ is active when A₁₅A₁₄A₁₃ = 010.
3. Start: 010 0 0000 0000 0000 = 4000H.
4. End: 010 1 1111 1111 1111 = 5FFFH.

Answer: 4000H to 5FFFH

Example 2 (GATE level: partial decoding). A 2K × 8 RAM uses A₀–A₁₀, and its CS′ is driven directly by A₁₅ (CS′ = A₁₅). A₁₁–A₁₄ are not connected. Find the number of mirror images and the full address space the chip occupies.

1. Unused high-order lines: A₁₁, A₁₂, A₁₃, A₁₄ → p = 4.
2. Mirror images = 2⁴ = 16.
3. Selected whenever A₁₅ = 0: 0000H to 7FFFH (32 KB), with the 2 KB repeated 16 times.
4. The lowest image is 0000H–07FFH; the next is 0800H–0FFFH, and so on.

Answer: 16 images, occupying 0000H–7FFFH

Example 3 (8255 and LED). (a) Write the 8255 control word for mode 0 with port A as input and ports B and C as outputs. (b) Find the series resistor for an LED (V_F = 2 V, I_F = 10 mA) driven from a 5 V port pin assumed to swing to the rail.

1. (a) D7 = 1 (I/O mode), D6D5 = 00, D4 = 1 (A in), D3 = 0 (upper C out), D2 = 0, D1 = 0 (B out), D0 = 0 (lower C out): 1001 0000.
2. (b) R = (5 − 2) / 0.010 = 300 Ω (use the next standard value, 330 Ω).

Answer: (a) 90H (b) 300 Ω (330 Ω standard)

Common mistakes

• Counting the address range end as start + size instead of start + size − 1.
• Forgetting mirror images when lines are left undecoded, then placing another device in an overlapping range.
• Mixing up memory-mapped and I/O-mapped I/O: in I/O-mapped I/O the 8085 uses IN/OUT with 8-bit port addresses.
• Wrong bit order in the 8255 control word, or forgetting D7 = 1 for I/O mode.
• Driving relays or multiple LEDs directly from port pins beyond their current rating.

For GATE IN

Expect: address range of a chip from a decoder circuit, chips and address lines in a memory system, mirror images under partial decoding, the function of ALE and latches, 8255 control words, I/O-mapped versus memory-mapped I/O, keypad line counts and current-limiting resistors. Practise writing each address line as a bit row to read ranges directly in hex.

Quick check

1. How many address lines are needed for 64 KB?
2. How many lines does a 4 × 4 matrix keypad need?
3. A 4K chip is selected with 2 of the 4 upper address lines unused. How many mirror images?
4. Which 8085 signal separates the low address byte from data?

Answers: 1. 16 2. 8 3. 4 4. ALE