VLSI Design Automation

Why it matters

Electronic design automation (EDA) makes large integrated circuits practical to implement, but results depend on correct specifications, constraints, libraries and review.

Key ideas

• RTL simulation checks behavior for exercised input sequences. Assertions and formal methods check stated properties under explicit assumptions; neither an unspecified testbench nor a passing simulation proves all possible behavior.
• Logic synthesis maps RTL into library cells under timing, area and power constraints.
• Placement, clock-tree synthesis and routing use optimization heuristics. They balance congestion, timing, power and area; a global optimum is not guaranteed.
• Static timing analysis checks constrained timing paths without enumerating all input sequences. Incorrect clock definitions or unjustified false paths can hide failures.
• DRC checks layout against process rules. LVS compares extracted connectivity with the intended schematic/netlist. Passing DRC alone does not establish functional correctness.
• Extraction, timing and power analysis after routing include interconnect effects. Sign-off uses required operating corners and variation assumptions.

Worked example

A register path has a 2.0 ns clock period, 0.12 ns maximum clock-to-Q delay, 1.65 ns combinational delay and 0.15 ns setup time. Assume zero clock skew and reserve 0.10 ns for uncertainty.

Setup slack = 2.0 − 0.12 − 1.65 − 0.15 − 0.10 = −0.02 ns. The path fails by 20 ps. If an implementation change reduces combinational delay to 1.55 ns, slack becomes +0.08 ns. Recheck hold timing, other paths, area and power before accepting the change.

Common mistakes

• Treating successful synthesis as proof of correctness.
• Applying timing exceptions merely to make reports pass.
• Ignoring unconstrained paths, parasitics or clock-domain crossings.
• Estimating EDA runtime with a universal tasks-per-second formula; runtime depends strongly on algorithms, design size and constraints.

Quick check

1. Does DRC prove that the circuit implements its specification?
2. What does negative setup slack mean?
3. Why repeat timing analysis after routing?

Answers: 1. No; it checks manufacturing rules. 2. The required setup constraint is violated. 3. Routed interconnect changes delay and loading.