Design for Testability

Why it matters

Design for Testability (DFT) is crucial in VLSI design because it ensures that integrated circuits (ICs) can be tested efficiently and effectively. This is important for identifying manufacturing defects and ensuring the reliability and performance of the ICs in real-world applications.

Key ideas

• Testability: The ease with which a circuit can be tested for defects. High testability means defects can be detected and diagnosed quickly.
• Built-In Self-Test (BIST): A technique where the circuit includes additional logic to test itself, reducing the need for external testing equipment.
• Scan Design: Involves adding scan chains to flip-flops in a circuit, allowing for easier control and observation of internal states during testing.
• Boundary Scan: A method standardized by IEEE 1149.1, allowing for testing of interconnections on PCBs using a serial test access port, reducing the need to probe individual board interconnections.
• Fault Models: Used to simulate potential defects in a circuit, such as stuck-at faults, bridging faults, and delay faults.

Formulas

• Fault Coverage = (Number of Detected Faults / Total Number of Faults) * 100
  • Fault Coverage: Percentage of faults detected.
  • Number of Detected Faults: Count of faults identified during testing.
  • Total Number of Faults: Total modeled faults in the stated fault list; this is not a count of actual manufacturing defects.

Worked example

Given: A circuit with 100 potential faults, of which 85 are detected during testing.

1. Calculate the fault coverage using the formula: Fault Coverage = (Number of Detected Faults / Total Number of Faults) * 100
2. Substitute the given values: Fault Coverage = (85 / 100) * 100
3. Calculate the result: Fault Coverage = 85%

Final Answer: 85%

Common mistakes

• Ignoring Fault Models: Not considering different fault models can lead to incomplete testing.
• Overlooking Scan Chain Design: Improper design of scan chains can result in inefficient testing.
• Neglecting Power Considerations: Testing can increase power consumption, which if not managed, can affect the circuit's performance.

Exam and interview preparation

Understand fault models, scan-chain controllability and observability. Treat this as supplementary VLSI material and check the official EC syllabus rather than assuming every DFT detail is examinable.

Reference: IEEE 1149.1 working group.

Quick check

1. What is the purpose of Built-In Self-Test (BIST) in VLSI?
2. How does boundary scan testing differ from traditional testing methods?
3. What is a common fault model used in VLSI testing?

Answers: 1. To allow the circuit to test itself. 2. It uses a test access port and boundary registers to control and observe board interconnections. 3. Stuck-at fault model.