Emerging Trends in VLSI

Why it matters

Modern VLSI improves systems through transistor structures, interconnect, packaging and architecture together. Smaller nominal process nodes do not automatically guarantee lower cost, higher clock speed or lower total power.

Key ideas

• FinFET and gate-all-around devices: Multiple gate surfaces improve electrostatic control compared with a planar transistor. Nanosheet gate-all-around structures further surround the channel. Performance still depends on process, voltage, leakage and interconnect.
• Chiplets and 2.5D integration: Separate dies can share a package and communicate through an interposer or other dense interconnect. This can combine different process technologies, with interface, assembly and test costs.
• 3D integration: Vertically connected dies shorten some connections and increase integration density. Thermal removal, power delivery, alignment, testability and yield remain design constraints.
• AI accelerators: Specialized arithmetic and data reuse can improve efficiency for suitable workloads. Memory bandwidth and movement energy may dominate; peak arithmetic throughput alone does not predict application performance.
• Emerging materials: Research results should be distinguished from qualified manufacturing processes. Promising carrier mobility alone does not establish a practical digital switch, manufacturability or circuit-level advantage.

Worked example: energy of data movement

For a link, dynamic communication power is approximately P = E_bit × R, where E_bit is energy per transferred bit in joules and R is bit rate in bits/s. Use consistent definitions that include the intended transmitter, receiver and interconnect costs.

At 2 pJ/bit and 256 Gbit/s, P = 2×10⁻¹² × 256×10⁹ = 0.512 W. At 0.5 pJ/bit and the same throughput, P = 0.128 W, a 75% reduction in this modeled link power. This does not imply a 75% reduction in total chip power; static power, computing and other links remain.

Common mistakes

• Treating a node name as a literal dimension shared by every transistor feature.
• Assuming stacking always improves thermal performance.
• Comparing peak TOPS without numerical precision, utilization and memory traffic.
• Presenting a research prototype or roadmap as an available production capability.

Exam preparation

Use this as technology context. Prioritize MOS devices, CMOS logic, timing and power fundamentals in the official EC syllabus; do not infer examination weight from industry publicity.

Quick check

1. Why can shorter die-to-die links save energy?
2. Name a challenge of 3D stacking.
3. Does 75% less link power mean 75% less system power?

Answers: 1. They can reduce capacitance and the energy required per bit. 2. Heat removal, power delivery or test/yield management. 3. No; other power components remain.

Further reading

• TSMC: nanosheet logic research
• TSMC: CoWoS 2.5D integration
• TSMC: SoIC 3D integration