Testing and Verification

Why it matters

Testing and verification in VLSI Design are crucial to ensure that integrated circuits (ICs) function correctly and reliably. With the increasing complexity of VLSI systems, thorough testing and verification help in identifying and rectifying design errors early, reducing time-to-market and cost.

Key ideas

• Verification: This is the process of checking whether a design meets the specifications and requirements. It involves simulation, formal verification, and equivalence checking.
• Testing: This involves checking the manufactured ICs for defects. It includes fault modeling, test pattern generation, and fault simulation.
• Fault Models: Common models include stuck-at faults, bridging faults, and delay faults, which help in understanding potential defects.
• Design for Testability (DFT): Techniques like scan chains and Built-In Self-Test (BIST) are used to make testing easier and more effective.
• Simulation: Used to verify the logical correctness of the design before fabrication.
• Formal Verification: Proves specified properties or equivalence within a model and assumptions; it does not automatically prove every aspect of a chip correct.

Formulas

• Fault Coverage = (Number of Detected Faults / Total Number of Faults) × 100
  • Fault Coverage: Percentage of faults detected.
  • Number of Detected Faults: Count of faults identified by the test.
  • Total Number of Faults: Total modeled faults in the defined fault list; not the number of actual physical defects in a manufactured chip.

Worked example

Given: A VLSI design has 1000 potential faults. A test detects 950 of these faults.

1. Calculate the fault coverage using the formula: Fault Coverage = (Number of Detected Faults / Total Number of Faults) × 100
2. Substitute the given values: Fault Coverage = (950 / 1000) × 100
3. Calculate: Fault Coverage = 95%

Answer: 95% of the specified modeled fault list. Fault coverage differs from functional/code coverage and manufacturing yield. State whether untestable faults are included or excluded in the denominator.

Common mistakes

• Ignoring Fault Models: Not considering different fault models can lead to incomplete testing.
• Overlooking DFT Techniques: Failing to incorporate DFT can make testing inefficient and costly.
• Inadequate Simulation: Relying solely on simulation without formal verification can miss corner cases.

For GATE EC

Questions often involve calculating fault coverage, understanding fault models, and applying DFT techniques. Practice problems on test pattern generation and fault simulation are beneficial.

Quick check

1. What is the purpose of verification in VLSI design?
2. Name two common fault models used in VLSI testing.
3. How is fault coverage calculated?

Answers: 1. To ensure the design meets specifications. 2. Stuck-at faults, bridging faults. 3. (Number of Detected Faults / Total Number of Faults) × 100.