Timing Analysis

Why it matters

Timing analysis checks whether data reaches storage elements early enough for setup and remains stable long enough for hold. Both conditions matter; slowing the clock generally helps setup but does not repair a same-edge hold violation.

Key ideas

Static timing analysis propagates timing bounds through constrained paths using cell/interconnect models and timing exceptions. It does not require functional input vectors, but correct constraints and corners are essential. Dynamic simulation checks the exercised input sequences and cannot by itself establish exhaustive timing coverage. Neither method is universally more accurate independent of models and assumptions.

Setup time is the required data-stable interval before capture; hold time is the interval after capture. Clock-to-Q is the launching register’s output delay. Combinational delay includes cells and wires. Skew is the difference in capture and launch clock arrival times.

Equations

Define skew s = t_capture − t_launch, positive when the capture clock arrives later. For a one-cycle register path, ignoring additional uncertainty:

T ≥ t_cq,max + t_comb,max + t_setup − s. t_cq,min + t_comb,min ≥ t_hold + s.

Positive skew helps setup but hurts hold under this convention. Clock jitter and uncertainty require additional margins. Hold time is not added to setup time to obtain clock period.

Worked example

Let t_cq,max = 0.8 ns, t_comb,max = 4 ns, t_setup = 0.7 ns, and s = +0.2 ns.

Minimum period from setup = 0.8+4+0.7−0.2 = 5.3 ns. Maximum frequency from this path = 1/(5.3 ns) ≈ 188.7 MHz.

For hold, let t_cq,min = 0.2 ns, t_comb,min = 0.15 ns and t_hold = 0.3 ns. Data arrives after 0.35 ns, but the requirement is 0.3+0.2 = 0.5 ns. Hold slack is 0.35−0.5 = −0.15 ns, so this path fails hold despite meeting setup at a 5.3 ns clock. At least 0.15 ns additional minimum-path delay would be needed in this simplified calculation; recheck setup and all corners after any fix.

Common mistakes

Adding setup, hold and skew without data-path delay; mixing maximum and minimum delays; changing skew sign mid-calculation; assuming lower clock frequency solves hold; and ignoring false/multicycle paths or asynchronous crossings without justified constraints.

Quick check

1. Does setup use maximum or minimum path delay?
2. Does hold use maximum or minimum path delay?
3. Under s = capture−launch, what does positive skew do?

Answers: 1. Maximum. 2. Minimum. 3. Helps setup and hurts hold.