Low Power VLSI Design

Why it matters

Low Power VLSI Design is crucial in the development of modern electronic devices, where power efficiency is a key factor. Reducing power consumption extends battery life in portable devices and reduces heat generation, improving reliability and performance.

Key ideas

• Power Dissipation: In VLSI circuits, power dissipation occurs mainly due to dynamic and static power. Dynamic power is associated with charging and discharging of capacitors, while static power is due to leakage currents.
• Dynamic Power Reduction: Techniques include reducing supply voltage, using clock gating, and optimizing switching activity.
• Static Power Reduction: Techniques involve using high-threshold voltage transistors and power gating.
• Multi-Threshold CMOS (MTCMOS): Utilizes transistors with different threshold voltages to optimize power and performance.
• Voltage Scaling: Reducing the supply voltage to decrease power consumption, often used in conjunction with frequency scaling.
• Adiabatic Computing: Specialized circuits recover some switching energy; their power-clock and speed constraints mean this is not a universal replacement for conventional CMOS.
• Clock gating reduces switching but does not remove leakage. Power gating reduces standby leakage and requires isolation, state-retention decisions and wake-up management. Lower supply voltage usually reduces achievable clock speed.

Formulas

• Dynamic Power: P_dynamic = α·C·V^2·f
  • α: Average number of 0-to-1 charging transitions per clock period (dimensionless)
  • C: Load capacitance (farads)
  • V: Supply voltage (volts)
  • f: Frequency of operation (hertz)
• Static Power: P_static = I_leakage·V
  • I_leakage: Leakage current (amperes)
  • V: Supply voltage (volts)

Worked example

Given: Load capacitance C = 10 pF, supply voltage V = 1.2 V, frequency f = 1 GHz, activity factor α = 0.5.

1. Calculate dynamic power using the formula: P_dynamic = α·C·V^2·f P_dynamic = 0.5·10×10^-12 F·(1.2 V)^2·1×10^9 Hz P_dynamic = 0.5·10×10^-12·1.44·10^9 P_dynamic = 7.2×10^-3 W

Dynamic Power = 7.2 mW

Common mistakes

• Ignoring leakage power in low-power designs, which can be significant in modern technologies.
• Overlooking the impact of temperature on leakage currents.
• Miscalculating the activity factor, leading to incorrect power estimations.

For GATE EC

Questions often involve calculating power dissipation using given parameters or comparing different power reduction techniques. Practice problems on dynamic and static power calculations, and understand the trade-offs in power reduction strategies.

Quick check

1. What is the primary source of dynamic power dissipation?
2. Name one technique to reduce static power.
3. What does MTCMOS stand for?

Answers: 1. Charging and discharging of capacitors. 2. Power gating. 3. Multi-Threshold CMOS.