Timers, counters and interrupts

Why it matters

Sampling a sensor every millisecond, measuring a shaft's speed from encoder pulses, generating a stepper's step train or running a control loop at a fixed rate all rely on hardware timers and interrupts. Software delay loops waste the CPU and drift; a timer plus an interrupt gives exact, repeatable timing while the processor does other work.

Key ideas

Timer vs counter. A timer/counter is a hardware register that increments (or decrements) on each input pulse. If the pulses come from the internal clock (through a prescaler), it is a timer — its count measures time. If they come from an external pin, it is a counter — its count measures events (bottles, encoder edges).

Prescaler. A divider between the clock and the timer. With a prescaler N_pre, one timer tick lasts N_pre/f_clk. A larger prescaler gives longer maximum intervals but coarser resolution.

Operating modes.

• Overflow (normal) mode: an n-bit timer counts up to 2ⁿ − 1, rolls over to 0 and sets an overflow flag. To get a chosen interval, preload the register so it overflows after the wanted number of ticks.
• Compare / CTC mode: the timer is compared with a compare register (OCR) every tick; on a match it sets a flag, can toggle a pin, and clears to 0. This gives an exact period with no software reload.
• Input capture: on an edge at a capture pin the current count is latched into a capture register — used to measure period, pulse width or speed.
• PWM: compare-match logic sets and clears a pin each period (next-but-one topic).

8051 timers. Timer 0 and 1 count machine cycles, f_osc/12 for the classic core (1 µs per tick at 12 MHz). Modes set in TMOD: mode 0 = 13-bit, mode 1 = 16-bit, mode 2 = 8-bit auto-reload (TH reloads TL — used for baud rates), mode 3 = Timer 0 split into two 8-bit timers. TR0/TR1 start them; TF0/TF1 are the overflow flags. Setting C/T = 1 makes it count pulses on the T0/T1 pin.

Interrupts. An interrupt is a hardware request that makes the CPU suspend the main program, save the return address (and on Cortex-M some registers), jump to an interrupt service routine (ISR) through a vector, and return afterwards.

• Sources: external pins (edge- or level-triggered), timer overflow/compare/capture, serial, ADC conversion complete, watchdog, and software interrupts/exceptions.
• Each source has an enable bit, a flag bit and usually a priority. A global enable must also be set.
• Polling vs interrupts: polling repeatedly checks a flag (simple, but wastes time and can miss short events); interrupts respond within a bounded latency.
• Latency = time from the event to the first ISR instruction; it depends on the instruction being completed, the hardware entry sequence, and any higher-priority ISR running.
• ISR rules: keep it short, no blocking delays or printing, clear the flag if the hardware does not, share data through volatile variables, and protect multi-byte shared data from being half-updated.

Watchdog timer. An independent timer that resets the MCU if software fails to "kick" it within its timeout — the standard recovery from a hung program in industrial products.

Connection to PLCs. PLC TON/TOF timers and CTU/CTD counters (later topics) are software timers built on the same idea: a time base and a count compared with a preset.

Formulas

T_tick = N_pre / f_clk

• T_tick = timer tick (s); N_pre = prescaler ratio; f_clk = timer input clock (Hz). For the classic 8051, f_clk = f_osc / 12.

T_max = 2ⁿ × T_tick

• Longest interval for an n-bit timer (s).

Preload = 2ⁿ − T_d / T_tick

• Value loaded for an overflow after delay T_d (s) in overflow mode; must be a non-negative integer.

f_int = f_clk / (N_pre × (OCR + 1)) → OCR = f_clk / (N_pre × f_int) − 1

• CTC (clear-on-match) interrupt frequency (Hz); OCR = compare register value.

Δ = (C₂ − C₁) mod 2ⁿ, T_sig = Δ × T_tick, f_sig = 1 / T_sig

• Input capture: C₁, C₂ = two captured counts (one rollover at most between them).

t_counter = N / f_pulse

• Time for an event counter to reach N counts at pulse rate f_pulse (Hz).

Worked examples

Example 1 (standard). A classic 8051 with a 12 MHz crystal must produce a 5 ms delay using Timer 0 in mode 1. Find TH0 and TL0.

1. T_tick = 12 / f_osc = 12 / 12 × 10⁶ = 1 µs.
2. Ticks needed = T_d / T_tick = 5 ms / 1 µs = 5000.
3. Preload = 2¹⁶ − 5000 = 65 536 − 5000 = 60 536 = 0xEC78.

Answer: TH0 = 0xEC, TL0 = 0x78 (5000 ticks to overflow).

Example 2 (GATE level). An ATmega has a 16 MHz clock and a 16-bit Timer1 with prescalers 1, 8, 64, 256 and 1024. (a) Choose the smallest prescaler that allows a 1 s CTC interrupt and find OCR1A. (b) With prescaler 8, an input-capture unit records rising edges of a sensor signal at counts 64 000 and then 3464 (the timer rolled over once). Find the signal frequency.

1. Ticks for 1 s with N_pre = 1: 16 × 10⁶ — far above 65 536. Minimum prescaler = 16 × 10⁶ / 65 536 = 244.1, so the smallest available is 256.
2. OCR1A = f_clk / (N_pre × f_int) − 1 = 16 × 10⁶ / (256 × 1) − 1 = 62 499 (fits below 65 535). Tick = 16 µs.
3. Capture: Δ = (3464 − 64 000) mod 65 536 = 5000 ticks.
4. T_tick = 8 / 16 × 10⁶ = 0.5 µs → T_sig = 5000 × 0.5 µs = 2.5 ms.
5. f_sig = 1 / 2.5 ms = 400 Hz.

Answers: prescaler 256, OCR1A = 62 499; signal frequency = 400 Hz.

Common mistakes

• Forgetting the +1 in CTC mode: the period is (OCR + 1) ticks because counting includes 0.
• Loading the delay count instead of 2ⁿ − count in overflow mode.
• Forgetting the 8051's divide-by-12 (classic core) — enhanced single-cycle derivatives differ, so check the datasheet.
• Ignoring rollover in input capture; use unsigned subtraction modulo 2ⁿ.
• Picking a prescaler that makes the required count exceed 2ⁿ − 1, or a non-integer count that causes drift.
• Long ISRs (delays, printf) that block other interrupts and the main loop.
• Forgetting the global interrupt enable, or forgetting to clear a flag that software must clear, so the ISR re-enters endlessly.

For GATE ME

Timers appear in mechatronics as numericals on tick time, preload and compare values, maximum delay for a given register width and prescaler, event counting rates and frequency measurement, and as concept MCQs on interrupts (polling vs interrupt, vectors, priority, edge vs level triggering, watchdog). Practise converting carefully between µs and ms and checking that every computed count fits the register width.

Quick check

1. A 16-bit timer runs at 16 MHz with prescaler 8. What is its overflow period?
2. For an 8051 at 12 MHz in mode 1, what preload gives a 50 ms delay?
3. In CTC mode at 16 MHz with prescaler 64, what OCR gives a 1 kHz interrupt?
4. What does a watchdog timer do?
5. Why is polling unsuitable for a 2 µs pulse on a busy MCU?

Answers: 1. 32.768 ms 2. 15 536 = 0x3CB0 3. 249 4. Resets the MCU if software fails to refresh it in time 5. The pulse may come and go between two polls; an edge interrupt latches it.