Microprocessor vs microcontroller; 8051 architecture

Why it matters

Almost every mechatronic product, from a washing machine to a CNC axis drive, has a small computer buried inside it that reads sensors and drives actuators. Choosing between a microprocessor and a microcontroller decides the board's cost, size and power, and the 8051 is still the reference architecture that university syllabi, viva questions and interviews use to test whether you understand memory maps, ports, timing and interrupts.

Key ideas

Microprocessor (MPU). A CPU on a chip: ALU, registers, control unit and bus interface. Program memory, data memory, timers and I/O are separate chips on the board. It is built for general-purpose, high-throughput computing (PCs, single-board computers running Linux).

Microcontroller (MCU). CPU + program memory (ROM/Flash) + data RAM + I/O ports + timers + serial port + interrupt controller on one chip. It is built for a dedicated control job, with low cost, low power, small board area and deterministic response to real-world events.

Feature	Microprocessor	Microcontroller
Memory and I/O	External	On-chip
Typical use	General computing	Dedicated control (embedded)
Board cost and size	Higher	Lower
Power	Higher	Low, with sleep modes
Instruction set	Rich, data-processing oriented	Bit-manipulation and I/O oriented

8051 architecture (classic Intel 8051, MCS-51 family).

• CPU: 8-bit ALU and data bus, accumulator A, register B (used by MUL and DIV), eight working registers R0–R7, program status word (PSW).
• Address registers: 16-bit program counter (PC) and 16-bit data pointer (DPTR), so each external space can address 2^16 = 64 KB.
• Memory (Harvard organisation): separate address spaces for program and data. On chip: 4 KB ROM and 128 bytes of RAM. Externally: up to 64 KB program memory (read with the PSEN strobe) and 64 KB data memory (accessed with MOVX, RD and WR strobes).
• Internal RAM map (00h–7Fh): 00h–1Fh four register banks of R0–R7 (bank chosen by RS1, RS0 in PSW); 20h–2Fh bit-addressable area (16 bytes = 128 bits, bit addresses 00h–7Fh); 30h–7Fh general scratch-pad. The stack pointer SP resets to 07h, so the first push goes to 08h.
• Special function registers (SFRs): at 80h–FFh (direct addressing only): ports P0–P3, TMOD, TCON, SCON, SBUF, IE, IP, PSW, SP, DPL, DPH and others. SFRs whose address ends in 0 or 8 are bit-addressable.
• I/O: 32 pins in four 8-bit ports. P0 is open-drain (needs external pull-ups when used as I/O) and carries the multiplexed low address/data bus AD0–AD7 when external memory is used; P2 gives the high address byte A8–A15; P3 pins have alternate functions (RXD, TXD, INT0, INT1, T0, T1, WR, RD).
• Control pins: ALE latches the low address byte from P0; EA = 1 means execute from internal ROM first, EA = 0 means fetch all code from external memory; RST is active high.
• Peripherals: two 16-bit timer/counters (Timer 0 and Timer 1), one full-duplex UART, and five interrupt sources (INT0, Timer 0, INT1, Timer 1, serial) with two programmable priority levels.
• PSW flags: CY (carry), AC (auxiliary carry), F0 (user flag), RS1 and RS0 (register bank select), OV (overflow), P (parity of A).

Timing. In the classic 8051 one machine cycle is 12 oscillator periods. Most instructions take 1 or 2 machine cycles; MUL and DIV take 4. Modern single-cycle 8051 derivatives use fewer clocks per machine cycle, so always check the data sheet of the part you use.

Connections. The timers, interrupts and UART introduced here are covered in detail in the timers/interrupts and serial-communication topics; Cortex-M and AVR are compared against this baseline in the next topic.

Formulas

T_osc = 1 / f_osc

• f_osc = crystal frequency (Hz), T_osc = oscillator period (s).

T_MC = 12 / f_osc (classic 8051)

• T_MC = machine-cycle time (s). For 12 MHz, T_MC = 1 µs.

t_instr = N_MC · T_MC

• N_MC = machine cycles taken by the instruction (from the instruction set table).

Memory locations = 2^n

• n = number of address lines. 16 lines → 65 536 locations (64 KB).

Bit address = 8·(byte address − 20h) + bit number

• For a bit in the bit-addressable RAM area 20h–2Fh; bit number 0–7.

Total delay = N_total · T_MC

• N_total = total machine cycles counted over every instruction executed in a delay loop.

Worked examples

Example 1 (standard). An 8051 runs from an 11.0592 MHz crystal. Find the machine-cycle time and the time taken by a 2-cycle instruction such as DJNZ.

1. Formula: T_MC = 12 / f_osc.
2. T_MC = 12 / (11.0592 × 10^6 Hz) = 1.0851 × 10^-6 s = 1.085 µs.
3. Formula: t_instr = N_MC · T_MC.
4. t = 2 × 1.085 µs = 2.17 µs.

(11.0592 MHz is chosen because it divides exactly into standard baud rates; it is not "faster" than 12 MHz.)

Example 2 (GATE level). A classic 8051 at 12 MHz runs this nested delay loop. MOV takes 1 machine cycle and DJNZ takes 2. Find the delay.

MOV R3,#250        ; 1 cycle, executed once
OUTER: MOV R2,#200 ; 1 cycle, executed 250 times
INNER: DJNZ R2,INNER ; 2 cycles, executed 200 times per outer pass
DJNZ R3,OUTER      ; 2 cycles, executed 250 times

1. T_MC = 12 / 12 MHz = 1 µs.
2. Cycles in one outer pass = 1 (MOV R2) + 200 × 2 (inner DJNZ) + 2 (outer DJNZ) = 403.
3. N_total = 1 + 250 × 403 = 1 + 100 750 = 100 751 cycles.
4. Delay = 100 751 × 1 µs = 100.751 ms ≈ 100.75 ms.

Example 3 (memory map). Find the bit address of bit 5 of internal RAM byte 25h, and the number of address lines needed for an 8 KB external data RAM.

1. Bit address = 8 × (25h − 20h) + 5 = 8 × 5 + 5 = 45 = 2Dh.
2. 8 KB = 8192 = 2^13, so 13 address lines (A0–A12) are needed.

Common mistakes

• Using the crystal period instead of the machine-cycle period: on a classic 8051 every instruction time contains the factor 12.
• Forgetting that a DJNZ loop body executes the loop count times, but the initialising MOV executes only once (or once per outer pass in a nested loop).
• Saying the 8051 has 256 bytes of RAM: the classic 8051 has 128 bytes; the 8052 adds another 128 bytes at 80h–FFh, reachable only by indirect addressing because direct addresses 80h–FFh select the SFRs.
• Forgetting the pull-up resistors on Port 0 when it is used as general I/O.
• Calling "Harvard" a claim that program and data share one bus internally; in the 8051 they are separate address spaces selected by different instructions (MOVC versus MOV/MOVX).
• Treating a microcontroller as just a "small microprocessor": the defining difference is on-chip memory and peripherals.

For GATE ME

• Conceptual MCQs/MSQs comparing microprocessors and microcontrollers, and recalling 8051 features: on-chip memory size, number of ports, timers and interrupt sources, Harvard organisation, role of ALE, PSEN and EA.
• NAT questions on machine-cycle time, instruction time and nested delay-loop counts; practise counting cycles carefully, including the instructions outside the loop.
• Address-space questions: memory size from address lines and vice versa, bit addresses in the bit-addressable area.

Quick check

1. What is the machine-cycle time of a classic 8051 with a 24 MHz crystal?
2. How many bit-addressable bits does the internal RAM area 20h–2Fh provide?
3. Which port must have external pull-ups when used as general I/O?
4. What does EA = 0 tell the 8051?
5. How many address lines does a 64 KB space need?

Answers: 1. 0.5 µs; 2. 128 bits; 3. Port 0; 4. Fetch all program code from external memory; 5. 16.