Flip-flops, counters and shift registers

Why it matters

Anything in a machine that must remember or count uses flip-flops: an encoder pulse counter on a motor shaft, a debounced push-button that toggles a conveyor, a frequency divider that makes a 1 Hz tick from a crystal, or a shift register that drives 16 LEDs from three microcontroller pins. Timing limits of these circuits decide how fast a counter can run before it miscounts.

Key ideas

Latches and flip-flops. Both are bistable elements that store one bit (Q, with complement Q′). A latch is level-sensitive: while its enable is active the output follows the inputs. A flip-flop is edge-triggered: it samples its inputs only at the active clock edge (rising or falling) and holds Q constant otherwise. Synchronous systems use flip-flops so that every state change happens at a known instant.

Basic SR latch. Two cross-coupled NOR gates (or NAND gates, with active-low inputs). S = 1 sets Q = 1, R = 1 resets Q = 0, S = R = 0 holds the state. S = R = 1 is not allowed: both outputs are forced to the same value, and when both inputs are released together the final state is unpredictable.

The four flip-flop types (behaviour at the active clock edge):

• SR: as the latch, with S = R = 1 forbidden.
• JK: like SR, but J = K = 1 toggles the output instead of being forbidden.
• D (data/delay): Q takes the value of D. The commonest type; registers are built from it.
• T (toggle): T = 1 toggles, T = 0 holds. A JK with J = K = T behaves as a T flip-flop. Asynchronous preset and clear inputs override the clock and are used for initialisation.

Race-around and master-slave. In a level-triggered JK with J = K = 1, the output keeps toggling for as long as the clock is high if the pulse is longer than the propagation delay. Master-slave construction (or true edge triggering) fixes this so the output changes once per clock.

Timing parameters. Setup time t_su (input must be stable before the edge), hold time t_h (stable after the edge) and clock-to-output delay t_pd. Violating setup or hold can leave the flip-flop metastable, which is why asynchronous inputs such as limit switches are passed through two flip-flops (a synchroniser) before use.

Counters.

• Ripple (asynchronous) counter: each flip-flop is a toggle stage clocked by the output of the previous one. Simple, but delays add up, and the outputs pass through false intermediate states (glitches) while the ripple settles. Each stage divides the frequency by 2, so stage k outputs f_clk/2ᵏ.
• Synchronous counter: every flip-flop shares the clock; gating logic decides which ones toggle. For a binary up counter with T flip-flops, T₀ = 1, T₁ = Q₀, T₂ = Q₀Q₁, and so on. All outputs change together, so it can run faster and is glitch-free.
• Mod-N counter: has N states. It needs ⌈log₂N⌉ flip-flops. A ripple mod-N counter is often made by clearing all flip-flops when state N is first reached (a decade counter clears on 1010); the state N appears only briefly.
• Up/down counters reverse the count with a control line; ring and Johnson counters are shift registers with feedback (below).

Shift registers. A chain of D flip-flops on a common clock; each clock moves the data one place. By input and output form: SISO (serial in, serial out; a delay of n clocks), SIPO (serial-to-parallel, used to expand outputs), PISO (parallel-to-serial, used to read many inputs), PIPO (a plain storage register). A ring counter feeds Q of the last stage back to the first and circulates a single 1, giving n states with n flip-flops. A Johnson (twisted-ring) counter feeds back the complement of the last stage and gives 2n states.

Formulas

SR: Q⁺ = S + R′·Q (with S·R = 0) JK: Q⁺ = J·Q′ + K′·Q D: Q⁺ = D T: Q⁺ = T ⊕ Q

• Q: present state; Q⁺: next state after the active clock edge.

Number of flip-flops n = ⌈log₂ N⌉ (mod-N counter) f_out = f_clk / N (output of a mod-N counter's last stage); f_out = f_clk / 2ⁿ for an n-bit binary counter

Ripple counter: f_max ≈ 1 / (n · t_pd)

• n: number of flip-flops; t_pd: clock-to-Q delay of one flip-flop (s). A conservative bound so the count settles within one clock period; add the decoding-gate delay if the outputs are decoded.

Synchronous counter: f_max = 1 / (t_pd + t_gate + t_su)

• t_gate: delay of the longest gate path between flip-flops (s); t_su: setup time (s).

Ring counter: N = n states; Johnson counter: N = 2n states

Worked examples

Example 1 (standard: decade ripple counter). A decade (mod-10) ripple counter is built from flip-flops with t_pd = 20 ns, driven by a 1 MHz clock. Find the number of flip-flops, the clearing logic, the frequency at the last stage and the maximum clock frequency.

1. n = ⌈log₂10⌉ = 4 flip-flops (Q₃Q₂Q₁Q₀).
2. The count must return to 0000 after 1001. State 1010 is the first with Q₃ = 1 and Q₁ = 1 together, so clear all stages with (Q₃·Q₁)′ applied to the active-low clear inputs.
3. f_out = f_clk/N = 1 MHz/10 = 100 kHz at Q₃.
4. f_max ≈ 1/(n·t_pd) = 1/(4 × 20 ns) = 1/(80 ns) = 12.5 MHz.

4 flip-flops, clear on Q₃·Q₁, Q₃ output 100 kHz, f_max ≈ 12.5 MHz.

Example 2 (GATE level: synchronous counter speed). A 3-bit synchronous binary up counter uses T flip-flops with t_pd = 15 ns and t_su = 5 ns. The AND gate that forms T₂ = Q₀·Q₁ has a delay of 5 ns. Find the toggle inputs and the maximum clock frequency.

1. T₀ = 1, T₁ = Q₀, T₂ = Q₀·Q₁ (a stage toggles when all lower bits are 1).
2. Longest path: clock edge → Q₀ (15 ns) → AND gate (5 ns) → T₂ must be stable t_su = 5 ns before the next edge.
3. Minimum period T_min = t_pd + t_gate + t_su = 15 + 5 + 5 = 25 ns.
4. f_max = 1/25 ns = 40 MHz.
5. Compare: a 3-bit ripple counter with the same flip-flops would be limited to about 1/(3 × 15 ns) ≈ 22.2 MHz, and its delay grows with every added bit while the synchronous figure barely changes.

T₀ = 1, T₁ = Q₀, T₂ = Q₀Q₁; f_max = 40 MHz.

Example 3 (GATE level: Johnson counter). A 4-bit Johnson counter (Q₀Q₁Q₂Q₃, shifting right, Q₀ fed with Q₃′) starts at 0000. Find its state after 6 clock pulses and its modulus.

1. Each clock: Q₀ ← Q₃′, Q₁ ← Q₀, Q₂ ← Q₁, Q₃ ← Q₂.
2. Sequence: 0000 → 1000 → 1100 → 1110 → 1111 → 0111 → 0011 → 0001 → 0000.
3. After 6 pulses the state is 0011; the sequence repeats after 8 states, so N = 2n = 8.

State 0011; mod-8 (2n with n = 4).

Common mistakes

• Calling a level-sensitive latch a flip-flop, and so missing the race-around problem.
• Using S = R = 1 in an SR flip-flop or forgetting that J = K = 1 toggles a JK.
• Taking the number of flip-flops for mod-N as log₂N without rounding up (mod-10 needs 4, not 3.32).
• Clearing a decade counter on 1001 instead of 1010; it would then count only 0–8.
• Applying the ripple f_max formula to a synchronous counter, or forgetting setup time in the synchronous one.
• Confusing ring (n states) and Johnson (2n states) counters.
• Reading the bit order of a shift register backwards when tracing serial data.

For GATE ME

Expect next-state questions for JK, D and T flip-flops, tracing a counter or shift register for a few clock pulses, counting states of ring and Johnson counters, finding the modulus of a counter with reset logic, frequency division, and maximum clock frequency of ripple and synchronous counters. Practise building a state table from a circuit and reading the sequence from it.

Quick check

1. A JK flip-flop has J = 1, K = 1 and Q = 0. What is Q after the clock edge?
2. How many flip-flops are needed for a mod-12 counter?
3. A 5-bit Johnson counter has how many states?
4. A 4-bit binary ripple counter is driven by 32 kHz. What is the frequency at the MSB?
5. Which shift register type converts serial data to parallel?

Answers: 1. 1. 2. 4. 3. 10. 4. 2 kHz. 5. SIPO.