ADC and DAC: types and resolution

Why it matters

Every mechatronic system crosses the analog–digital boundary twice: sensors (thermocouples, strain gauges, encoders with analog outputs, current shunts) are read by an ADC, and actuator commands (valve positions, motor speed references, audio) leave the controller through a DAC or PWM. Choosing the number of bits, the converter type and the sampling rate decides whether a control loop sees the signal it needs or a coarse, aliased version of it.

Key ideas

Sampling and quantisation. An ADC does two things: it samples the input at discrete instants (a sample-and-hold freezes the voltage while it is converted) and it quantises each sample to one of 2ⁿ codes for an n-bit converter.

• To avoid aliasing, the sampling frequency must exceed twice the highest frequency in the input (Nyquist criterion). In practice an analog anti-aliasing low-pass filter is placed before the ADC and f_s is chosen well above 2·f_max.
• A frequency above f_s/2 does not disappear; it folds back and appears as a false lower frequency that no digital filter can remove later.

Resolution and LSB. For a full-scale input range V_FS (usually equal to V_ref for a unipolar converter), one least significant bit is V_FS/2ⁿ. This is the smallest change the ADC can distinguish, or the smallest step a DAC can produce. Resolution is often quoted simply as "n bits" or as a percentage, 100/2ⁿ %.

• An ideal n-bit DAC with reference V_ref spans 0 to V_ref·(1 − 2⁻ⁿ): the all-ones code is one LSB below V_ref.
• Some textbooks define the step as V_max/(2ⁿ − 1), where V_max is the largest actual output. Both are used in exams; read which quantity the question gives (reference/full-scale or maximum output) and say which you used.

Quantisation error. Because a range of inputs maps to one code, the digital value differs from the true input by up to 1 LSB (truncating converter) or ±½ LSB (rounding converter, transitions offset by half an LSB). This error behaves like noise; for a full-scale sine wave the ideal signal-to-quantisation-noise ratio is about 6.02·n + 1.76 dB, so each extra bit buys about 6 dB.

ADC types.

• Flash (parallel): 2ⁿ − 1 comparators compare the input with a resistor-divider ladder at once; a priority encoder produces the code. Conversion in one clock, so it is the fastest type, but comparator count doubles with each bit, so it is limited to about 6–8 bits (video, oscilloscopes, radar).
• Successive approximation (SAR): an internal DAC and one comparator perform a binary search, deciding one bit per clock from MSB to LSB; conversion takes about n clock cycles. The usual choice for 8–18 bits at kS/s to a few MS/s; this is the ADC in most microcontrollers.
• Counter (digital ramp): a counter drives a DAC upward until it crosses the input; conversion time varies with input and is up to 2ⁿ − 1 clocks. Simple but slow; tracking versions follow slowly changing inputs.
• Dual-slope (integrating): the input is integrated for a fixed count, then a reference of opposite polarity is integrated until the output returns to zero; the second count is proportional to V_in. The result is independent of the RC value and the clock frequency, and choosing the fixed integration time as a multiple of 20 ms rejects 50 Hz mains hum. Slow (tens of conversions per second), used in digital multimeters.
• Sigma-delta (Σ-Δ): a 1-bit modulator samples at a very high rate, noise shaping pushes quantisation noise to high frequencies, and a digital decimation filter removes it, giving 16–24 bits at low to moderate bandwidths (audio, weighing scales, precision sensors).

DAC types.

• Binary-weighted resistor: bit k drives a resistor proportional to 2⁻ᵏ into an op-amp summing junction. Simple in principle but needs a resistor spread of 2ⁿ⁻¹ : 1, which is hard to make accurately for more than about 6–8 bits.
• R-2R ladder: uses only two resistor values, R and 2R. Each node of the ladder halves the current, so bit currents are binary-weighted automatically. Easy to match on a chip, hence the most common resistive DAC.
• Real DACs have settling time, offset, gain error and non-linearity (DNL, INL). A DAC is monotonic if its output never decreases when the code increases, which matters inside a control loop.

Connections. The comparator is the op-amp circuit of the previous topic; the SAR register, counters and encoders come from the digital topics; and PWM output from a microcontroller, after a low-pass filter, is a cheap DAC.

Formulas

LSB = V_FS / 2ⁿ

• V_FS: full-scale range (V), usually V_ref for a unipolar converter; n: number of bits. Gives the step size for both ADC and DAC.

D = int(V_in / LSB) (truncating ADC)

• D: output code (decimal); V_in: input (V), 0 ≤ V_in < V_FS.

V_o = V_ref · D / 2ⁿ (ideal unipolar DAC; magnitude)

• For an R-2R ladder feeding an inverting op-amp with feedback resistor R_f = R, V_o = −V_ref · D / 2ⁿ.

V_o = −V_ref · (R_f / R) · Σ b_k · 2⁻ᵏ, k = 0 (MSB) … n − 1 (weighted-resistor DAC, MSB resistor R)

• b_k: bit value (0 or 1); R_f: feedback resistor (Ω).

Quantisation error ≤ ½ LSB (rounding) or < 1 LSB (truncation)

SQNR ≈ 6.02·n + 1.76 (dB), ideal n-bit converter, full-scale sine input

f_s > 2·f_max (Nyquist); f_s: sampling frequency (Hz), f_max: highest input frequency (Hz)

t_conv ≈ n / f_clk (SAR); t_conv,max ≈ (2ⁿ − 1) / f_clk (counter type); flash needs 2ⁿ − 1 comparators.

Worked examples

Example 1 (standard: ADC code). A 10-bit truncating ADC has a 0–5 V input range. Find the LSB and the output code for V_in = 3.30 V.

1. LSB = V_FS / 2ⁿ = 5 / 1024 = 4.883 mV.
2. V_in / LSB = 3.30 / 0.004883 = 675.84.
3. Truncating: D = 675 (decimal) = 10 1010 0011 (binary).
4. Quantisation error = 3.30 − 675 × 0.004883 = 0.84 LSB ≈ 4.1 mV (less than 1 LSB, as expected).

LSB = 4.88 mV; code = 675 = 1010100011₂.

Example 2 (GATE level: choosing an ADC). A temperature transmitter gives 0–5 V for 0–100 °C. The controller must resolve 0.05 °C. A SAR ADC with 0–5 V range and a 2 MHz clock (one bit per clock) is used. Find (a) the minimum number of bits, (b) the actual resolution in °C, (c) the maximum sampling rate and the highest signal frequency that can be sampled without aliasing, (d) the ideal SQNR.

1. Levels needed = 100 °C / 0.05 °C = 2000. 2¹⁰ = 1024 is too few; 2¹¹ = 2048 is enough, so n = 11.
2. LSB = 5 / 2048 = 2.441 mV, which corresponds to 100/2048 = 0.0488 °C.
3. t_conv = n / f_clk = 11 / (2 × 10⁶) = 5.5 μs, so f_s,max = 1/5.5 μs = 181.8 kS/s (ignoring acquisition time).
4. Highest alias-free input frequency < f_s / 2 = 90.9 kHz.
5. SQNR = 6.02 × 11 + 1.76 = 67.98 dB.

n = 11 bits, resolution 0.0488 °C, f_s up to 181.8 kS/s, f_max below 90.9 kHz, SQNR ≈ 68.0 dB.

Example 3 (DAC output). An 8-bit R-2R DAC with V_ref = 10 V drives an inverting op-amp with R_f = R. Find the output for input 10110100 and the full-scale output.

1. D = 10110100₂ = 128 + 32 + 16 + 4 = 180.
2. V_o = −V_ref · D / 2ⁿ = −10 × 180 / 256 = −7.031 V.
3. Full scale (D = 255): V_o = −10 × 255 / 256 = −9.961 V.

V_o = −7.03 V; full-scale output −9.96 V.

Common mistakes

• Dividing by 2ⁿ when the question gives the maximum output voltage (that convention uses 2ⁿ − 1), or the reverse; check which voltage is given.
• Thinking an n-bit DAC can output exactly V_ref; the top code gives V_ref·(1 − 2⁻ⁿ).
• Saying sampling at exactly 2·f_max is enough; it must be greater, and real systems need an anti-aliasing filter and margin.
• Confusing resolution (step size) with accuracy (how close the output is to the true value, including offset, gain and linearity errors).
• Stating flash comparators as 2ⁿ instead of 2ⁿ − 1, or SAR conversion time as 2ⁿ clocks instead of n.
• Forgetting the minus sign at the output of an inverting summing amplifier.

For GATE ME

Expect short numericals: step size or percentage resolution, output voltage for a given binary input to an R-2R or weighted-resistor DAC, the code an ADC produces for a given input, number of bits for a required resolution, conversion time of SAR, counter and flash types, comparator count for a flash ADC and minimum sampling rate. Conceptual questions compare ADC types by speed, resolution and cost. Practise binary-to-decimal conversion quickly and keep track of the 2ⁿ versus 2ⁿ − 1 convention.

Quick check

1. What is the LSB of an 8-bit ADC with a 2.56 V full-scale range?
2. How many comparators does a 4-bit flash ADC need?
3. How many clock cycles does a 12-bit SAR ADC need per conversion (one bit per clock)?
4. Which ADC type rejects 50 Hz mains interference by its integration period?
5. A signal contains components up to 4 kHz. What is the minimum theoretical sampling rate?

Answers: 1. 10 mV. 2. 15. 3. 12. 4. Dual-slope (integrating) ADC. 5. Just above 8 kHz (8 kS/s is the Nyquist rate).