Computer Organization

Machine instructions define the operations a CPU can perform. Addressing modes determine how operands are located. GATE tests instruction formats, effective address calculation, and addressing mode trade-offs.

Cache memory bridges the speed gap between CPU and main memory. GATE tests cache mappings (direct, set-associative, fully associative), replacement policies, and average access time calculations.

Pipelining overlaps execution of multiple instructions to improve throughput. GATE tests pipeline stages, speedup, and the three types of hazards with their solutions.

I/O systems connect the CPU to peripheral devices. GATE tests I/O techniques (programmed, interrupt-driven, DMA), interrupt handling, and bus architecture.