Machine Instructions & Addressing Modes
Machine instructions define the operations a CPU can perform. Addressing modes determine how operands are located. GATE tests instruction formats, effective address calculation, and addressing mode trade-offs.
Key Points
- ·Instruction format: opcode + operand fields; variable or fixed length
- ·Immediate: operand is the value itself — fast, limited range
- ·Register: operand in a register — fastest, limited number of registers
- ·Direct: address field contains memory address — one memory access
- ·Indirect: address field contains address of address — two memory accesses
- ·Register Indirect: register holds memory address — one memory access after register fetch
- ·Indexed: EA = base register + offset (index) — used for array access
- ·PC-relative: EA = PC + displacement — used for branch instructions
What is Computer Organization?
Analogy: If the algorithm (software) is the recipe, computer organization is the kitchen equipment — how the processor (chef) is built, how it stores ingredients (memory), and how it communicates with other appliances (I/O devices).
Machine Instructions — The CPU's Language
The CPU only understands binary instructions. Each instruction has:
┌──────────────┬─────────────────────────────┐
│ Opcode │ Operand(s) │
│ (what to do) │ (where to find the data) │
└──────────────┴─────────────────────────────┘
Example (simple instruction):
ADD R1, R2, R3 → R1 = R2 + R3
Opcode: ADD
Operands: destination R1, source R2, source R3
Instruction address formats:
Zero-address (stack machine): ADD (operands implicitly popped from stack)
One-address (accumulator): ADD M (ACC = ACC + Mem[M])
Two-address: ADD R1, R2 (R1 = R1 + R2)
Three-address: ADD R1, R2, R3 (R1 = R2 + R3)
More addresses → shorter programs, more complex instructions
Fewer addresses → simpler hardware, longer programs
Addressing Modes — Where Is the Data?
Analogy: Think of addressing modes like different ways to tell someone where to find a book: - "Here is the book" (Immediate) — you hand it directly - "It is on shelf 5" (Direct) — go to that location - "The shelf number is written in the first drawer" (Indirect) — two lookups - "On the shelf right next to shelf 5" (Indexed) — base + offset
Mode │ How to find operand │ Memory accesses
────────────────┼────────────────────────────┼────────────────
Immediate │ Value IS in instruction │ 0 (fastest!)
Register │ Value IS in a register │ 0
Direct │ Instruction has address │ 1
Register │ Register has the address │ 1
Indirect │ → go to that address │
Indirect │ Instruction has address A │ 2 (slowest!)
│ → Mem[A] has actual address│ → Mem[Mem[A]]
Indexed │ EA = Reg + Displacement │ 1 (great for arrays!)
PC-relative │ EA = PC + Displacement │ 1 (used for branches)
Detailed Examples:
LOAD R1, #100 → R1 = 100 (Immediate: # means "the value")
LOAD R1, R2 → R1 = R2 (Register: copy from R2)
LOAD R1, 200 → R1 = Mem[200] (Direct: go to address 200)
LOAD R1, (R2) → R1 = Mem[R2] (Register Indirect: R2 holds address)
LOAD R1, (200) → R1 = Mem[Mem[200]] (Indirect: double lookup)
LOAD R1, 4(R2) → R1 = Mem[R2 + 4] (Indexed: great for A[i] = Mem[base + i*4])
BRANCH +50 → PC = PC + 50 (PC-relative: relative jump)
RISC vs CISC
RISC (Reduced Instruction Set Computer):
Philosophy: Simple, fast instructions. Do one thing per instruction.
Properties:
✓ Fixed-length instructions (32 bits typically)
✓ Load-Store architecture: ONLY load/store instructions access memory
(arithmetic instructions work ONLY on registers)
✓ Many general-purpose registers (32+)
✓ Pipelining-friendly (uniform instruction length and stages)
✓ Simple addressing modes
Examples: MIPS, ARM, RISC-V
CISC (Complex Instruction Set Computer):
Philosophy: One instruction can do the work of many.
Properties:
✓ Variable-length instructions (1-15 bytes in x86)
✓ Memory operands allowed in arithmetic (ADD [addr], R1)
✓ Many addressing modes
✗ Harder to pipeline (instructions have different lengths and durations)
✗ Fewer programmer-accessible registers
Examples: x86, x86-64 (Intel/AMD PCs)
Modern reality: x86 processors internally translate CISC instructions
to RISC-like micro-operations (micro-ops)!
Endianness — Byte Order in Memory
32-bit value: 0x12345678
Address | Big Endian | Little Endian
(lowest) | (MSB first) | (LSB first)
100 | 12 | 78
101 | 34 | 56
102 | 56 | 34
103 | 78 | 12
Big endian: natural reading order (most significant first)
Used by: SPARC, older MIPS, network protocols
Little endian: least significant byte at lowest address
Used by: x86, ARM (by default)
Memory trick: "Big endian = Big end of a number goes to the start (lowest address)"
Quick Check
Q1. Instruction LOAD R1, @500 uses indirect addressing. How many memory accesses? Answer: 2 — first access Mem[500] to get the actual address, second access that address to get the data.
Q2. What addressing mode is used for array access like A[i]? Answer: Indexed (Base + Displacement). EA = base register (pointing to start of A) + offset register (i × element_size). One memory access.
Q3. Why does RISC prefer load-store architecture? Answer: Separating memory accesses (load/store) from arithmetic operations simplifies pipeline design. Arithmetic stages are uniform — no stage needs to access memory except dedicated load/store stages.
Key Formulas
- Indexed EA: EA = Base_Register + Displacement
- PC-relative EA: EA = PC + Displacement (calculated from next instruction)
- Indirect EA: EA = Mem[address_field] — requires 2 memory accesses
GATE Exam Tips
- ★Indirect addressing requires TWO memory accesses — this is a very common GATE trap.
- ★RISC uses load-store: arithmetic instructions only use registers, never directly access memory.
- ★PC-relative addressing: displacement calculated from NEXT instruction (not current).
- ★Immediate mode has zero memory accesses — fastest for constants but limited range.
Finished reading this topic?
Mark it complete to track your study progress.