I/O Systems & Interrupts

I/O — Connecting CPU to the World

Analogy: - Polling: Like a waiter who checks every table every 30 seconds asking "Are you ready to order?" — wastes the waiter's time even when nobody is ready. - Interrupts: Like a buzzer at each table — the waiter only goes when called. Much more efficient! - DMA: Like having a self-service food station — customers (devices) take food (data) directly without the waiter (CPU) being involved.

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Three I/O Techniques

1. Programmed I/O (Polling)

CPU continuously checks status register of I/O device:

while (device_status_register != READY);  // busy wait
data = device_data_register;
write_to_memory(data);

Advantages: Simple, predictable timing
Disadvantages: CPU 100% busy — cannot do other work
               Wastes CPU cycles while waiting for slow device

When useful: Very fast devices where polling delay is acceptable

2. Interrupt-Driven I/O

CPU initiates I/O, then continues other work.
Device signals CPU (interrupt) when transfer is ready.

Flow:
1. CPU sends command to device controller
2. CPU continues executing other program
3. Device completes, asserts interrupt signal
4. CPU finishes current instruction
5. CPU saves state (PC, registers → stack)
6. CPU jumps to Interrupt Service Routine (ISR)
7. ISR reads data, acknowledges interrupt
8. CPU restores state, returns to interrupted program

Advantages: CPU can do useful work while waiting
Disadvantages: Overhead of saving/restoring state on each interrupt
               High interrupt rate → excessive overhead (interrupt storm)

Interrupt Latency = time from interrupt signal to start of ISR

Priority Handling:

Daisy Chain: devices connected in series to CPU
  Device1 → Device2 → Device3 → CPU
  Device1 has highest priority (closest to CPU)
  When multiple interrupts: Device1 gets served first

Parallel (Vectored): each device has own interrupt line
  Priority encoder selects highest-priority device
  Device provides vector (ISR address) → direct jump to correct ISR

3. DMA (Direct Memory Access)

For large data transfers (disk, network), involving CPU for every byte is wasteful.
DMA controller handles the transfer independently.

Setup:
1. CPU programs DMA controller:
   - Source address (device buffer or disk sector)
   - Destination address (RAM location)
   - Number of bytes to transfer
2. CPU issues command and continues other work
3. DMA controller takes the bus (one or more cycles at a time)
4. DMA transfers data directly from device → RAM
5. DMA signals completion interrupt to CPU
6. CPU processes the transferred data

DMA takes the BUS from CPU — "Cycle Stealing"
  CPU is stalled briefly for each stolen bus cycle
  But only during bus use, not during all computation

Burst Mode vs Cycle Stealing:

Cycle stealing: DMA takes ONE bus cycle, then returns bus to CPU
  CPU stalls one cycle per word transferred
  Interleaved with CPU activity — minimal disruption

Burst mode: DMA takes bus for ENTIRE transfer
  CPU completely blocked until DMA finishes
  Faster DMA transfer but CPU delayed more

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Comparison Table

Technique	CPU involvement	Efficiency	When to use
Polling	100% — busy wait	Low	Simple, fast devices
Interrupt-driven	Only on completion	Medium	Infrequent I/O
DMA	Setup + completion	High	Large bulk transfers

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Bus Architecture

Bus = shared communication channel connecting CPU, memory, I/O devices

Bus lines:
  Address bus: specifies memory or I/O address
  Data bus:    carries data being transferred
  Control bus: signals like READ/WRITE, interrupt, clock

Bus width: 32-bit or 64-bit (data transferred per cycle)

Synchronous vs Asynchronous Bus:

Synchronous:
  All transfers governed by common clock
  Simple, fast — every device must respond within fixed cycles
  Problem: clock frequency limited by slowest device on bus

Asynchronous:
  Uses REQ/ACK handshaking
  Sender: assert REQ
  Receiver: when ready, assert ACK
  Sender: de-assert REQ
  Receiver: de-assert ACK
  Adapts to any device speed — more complex but flexible

Bus Bandwidth:

Bandwidth = (bus_width_bytes × bus_frequency) / cycles_per_transfer

Example: 32-bit bus, 100 MHz, 4 cycles per transfer
Bandwidth = (4 bytes × 100,000,000) / 4 = 100 MB/s

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Memory-Mapped vs Port-Mapped I/O

Memory-Mapped I/O:
  Device registers appear in the normal memory address space
  Same LOAD/STORE instructions used for both memory and I/O
  Simple, no special instructions needed
  Used by: RISC architectures (ARM, MIPS)

Port-Mapped (Isolated) I/O:
  Separate I/O address space
  Special IN/OUT instructions (as in x86)
  Normal memory instructions cannot access I/O devices
  Used by: x86

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Quick Check

Q1. Which I/O technique maximises CPU utilisation for a disk transfer? Answer: DMA. The CPU only programs the DMA controller (quick) and processes data after completion (quick). The actual transfer happens without CPU involvement.

Q2. In DMA cycle stealing, what happens to the CPU? Answer: The CPU is stalled for one bus cycle each time the DMA steals a cycle to transfer a word. The CPU is NOT blocked for the entire transfer — it continues between stolen cycles.

Q3. A bus has 64-bit data width, 800 MHz, 2 cycles per transfer. What is the bandwidth?

Bandwidth = (8 bytes × 800,000,000) / 2 = 3200 MB/s = 3.2 GB/s