Memory Interfacing

Why it matters

Memory interfacing is crucial in microprocessors and embedded systems as it allows the processor to communicate with memory devices, enabling data storage and retrieval. This is essential for executing programs and handling data efficiently in real-time applications.

Key ideas

• Memory Types: Understand the difference between RAM (Random Access Memory) and ROM (Read-Only Memory). RAM is volatile and used for temporary data storage, while ROM is non-volatile and used for permanent data storage.
• Address Bus: The address bus carries the address from the processor to the memory. The width of the address bus determines the maximum addressing capability.
• Data Bus: The data bus transfers data between the processor and memory. Its width affects the amount of data transferred at a time.
• Control Signals: Control signals like Read/Write enable the processor to perform operations on memory.
• Memory Mapping: This involves assigning specific addresses to memory locations, allowing the processor to access them efficiently.
• Chip Select Logic: Used to enable a specific memory chip among multiple chips connected to the processor.

Formulas

• Memory Size = 2^n where n address bits select 2^n locations; capacity is in bytes only for byte-addressable memory.
• Number of Chips = Total Memory Size / Chip Memory Size where both memory sizes are in bytes.

Worked example

Given: A byte-addressable processor with an 8-bit data bus and 16-bit address bus and a requirement to interface with 32 KiB of RAM.

1. Calculate the maximum addressable memory:

   • Formula: Memory Size = 2^n
   • Calculation: Memory Size = 2^16 = 65536 bytes = 64 KiB

2. Determine the number of RAM chips needed:

   • Given each RAM chip is 8K × 8 bits (8 KiB).
   • Formula: Number of Chips = Total Memory Size / Chip Memory Size
   • Calculation: Number of Chips = 32 KiB / 8 KiB = 4

Final Answer: 4 RAM chips are needed.

For a 32 KiB block mapped to 0000H–7FFFH, A15 = 0 enables the RAM region, A14:A13 select one of four 8 KiB chips, and A12:A0 address within each chip. Decode read/write enables and verify timing so only the intended device drives the data bus.

Common mistakes

• Confusing the width of the data bus with the address bus, leading to incorrect memory size calculations.
• Forgetting to consider the control signals necessary for proper memory interfacing.
• Miscalculating the number of memory chips required due to incorrect unit conversions.

For GATE EC

• Questions often involve calculating the maximum addressable memory given the address bus width.
• Practice problems on determining the number of memory chips required for a given memory size.
• Be prepared to solve questions on memory mapping and chip select logic.

Quick check

1. What is the maximum memory size addressable by a 20-bit address bus?
2. How many 16 KiB memory chips are needed to create a 64 KiB memory system?
3. What is the role of control signals in memory interfacing?

Answers: 1. 1 MiB 2. 4 chips 3. They enable read/write operations.