Interrupts and Interrupt Handling

Why it matters

Interrupts are crucial in microprocessors and embedded systems as they allow the processor to respond with architecture-dependent latency to important events, improving efficiency and responsiveness. They enable multitasking by allowing a system to handle asynchronous events without polling, which conserves processing power and reduces latency.

Key ideas

• Interrupts: Signals that inform the processor of an event that needs immediate attention. They can be hardware or software interrupts.
• Interrupt Handling: The process of responding to an interrupt, which involves saving the current state, executing an interrupt service routine (ISR), and restoring the state.
• Interrupt Vector Table (IVT): A table that holds the addresses of ISRs. When an interrupt occurs, the processor uses the IVT to find the ISR address.
• Maskable and Non-Maskable Interrupts: Maskable interrupts can be ignored or delayed by the processor, while non-maskable interrupts are not blocked by the ordinary mask mechanism, but still have architectural recognition and service rules.
• Priority: Determines the order in which multiple interrupts are handled. Higher priority interrupts can preempt lower priority ISRs only when nesting/preemption is enabled and supported.

Formulas

• No specific formulas are typically associated with interrupts and interrupt handling, as it is more about understanding the process and architecture.

Worked example

Assume interrupts INT0 and INT1 are enabled, both are pending before the processor arbitrates, and INT0 has higher priority. INT0 is serviced first, followed by INT1 when eligible.

If INT1 instead arrives first and its ISR has already started before INT0 arrives, the order depends on nesting. With higher-priority preemption enabled, INT0 can interrupt INT1; after INT0 completes, INT1 resumes. Without nesting, INT0 waits until INT1 finishes. Priority alone does not reverse an ISR that already ran.

Interrupt latency is time from the request to the beginning of useful ISR execution; it includes recognition, masking/blocking, current-instruction completion and entry overhead. Keep handlers bounded, preserve required context and acknowledge the interrupt source correctly.

Common mistakes

• Confusing maskable and non-maskable interrupts.
• Forgetting to save and restore the processor state during ISR execution.
• Mismanaging interrupt priorities, leading to incorrect ISR execution order.

For GATE EC

Questions often involve understanding the sequence of interrupt handling, priority management, and distinguishing between different types of interrupts. Practice identifying and managing interrupt priorities and understanding the role of the IVT.

Quick check

1. What is an interrupt?
2. How does a processor determine which ISR to execute?
3. What is the difference between maskable and non-maskable interrupts?

Answers: 1. A signal for immediate attention. 2. By its architecture’s vector, fixed entry or dispatch mechanism. 3. Maskable can be ignored; non-maskable cannot.