Sequential Circuits — Flip-Flops & State Machines
Sequential circuits have memory; outputs depend on current inputs AND past state. GATE tests flip-flop types, state diagrams, state tables, and Moore vs Mealy machines.
Key Points
- ·SR latch: basic memory element; S=R=1 is forbidden state
- ·D flip-flop: Q(t+1) = D; simplest, used in registers; eliminates SR forbidden state
- ·JK flip-flop: J=K=1 → toggle; versatile, no forbidden state
- ·T flip-flop: T=1 → toggle, T=0 → hold; used in counters
- ·Edge-triggered: changes state on clock edge (rising or falling), not level
- ·Moore machine: output depends only on current state; Mealy: output depends on state AND input
- ·Mealy has fewer states than equivalent Moore; Mealy responds one clock earlier
- ·State minimisation: merge equivalent states (same output, same next state for all inputs)
- ·Synchronous counter: all flip-flops clocked simultaneously; asynchronous (ripple): cascaded
Sequential Circuits — The Memory Circuits
Analogy: A combinational circuit is like a calculator — give it numbers, get an answer, no history. A sequential circuit is like a video game — its output depends on what buttons you pressed NOW and ALL THE PREVIOUS buttons you pressed (the game state).
Latches — Level-Sensitive Memory
SR Latch (Set-Reset)
S=1, R=0 → Set Q to 1
S=0, R=1 → Reset Q to 0
S=0, R=0 → Hold (keep current Q)
S=1, R=1 → FORBIDDEN (Q and Q' both try to be 1 → undefined!)
| S | R | Q(t+1) |
|---|---|---------|
| 0 | 0 | Q(t) | Hold
| 0 | 1 | 0 | Reset
| 1 | 0 | 1 | Set
| 1 | 1 | FORBIDDEN|
Latch vs Flip-Flop:
Latch: Level-sensitive — output can change ANYTIME while enable=1
Flip-flop: Edge-triggered — output changes ONLY on clock edge (rising ↑ or falling ↓)
Much more predictable in digital systems
Flip-Flops — The Memory Atoms
D Flip-Flop (Data / Delay)
Analogy: A snapshot camera — captures the input value exactly when the clock fires.
Q(t+1) = D (output = data input on clock edge)
No forbidden state! The simplest flip-flop.
Used in: registers, pipeline stages, data storage
| D | Q(t+1) |
|---|--------|
| 0 | 0 |
| 1 | 1 |
JK Flip-Flop (Jack-King)
Analogy: Improved SR — fixes the forbidden state by making J=K=1 mean "toggle."
| J | K | Q(t+1) |
|---|---|-------------|
| 0 | 0 | Q(t) Hold |
| 0 | 1 | 0 Reset |
| 1 | 0 | 1 Set |
| 1 | 1 | Q'(t) Toggle|
Characteristic equation: Q(t+1) = JQ' + K'Q
Converting JK to D: J = D, K = D'
Converting JK to T: J = T, K = T
T Flip-Flop (Toggle)
Analogy: A light switch with one button. Press it: light goes ON. Press again: light goes OFF.
| T | Q(t+1) |
|---|--------------|
| 0 | Q(t) Hold |
| 1 | Q'(t) Toggle |
Characteristic equation: Q(t+1) = T ⊕ Q
Perfect for COUNTERS: connect T=1 always → toggles every clock cycle
Counters — Counting with Flip-Flops
Asynchronous (Ripple) Counter
Chain of T flip-flops (T=1) where each FF clock = previous FF output
CLK → [FF₀] → [FF₁] → [FF₂]
Q₀ Q₁ Q₂
FF₀ toggles every clock cycle
FF₁ toggles when FF₀ goes from 1→0 (falling edge)
FF₂ toggles when FF₁ goes from 1→0
Output Q₂Q₁Q₀ counts: 000, 001, 010, 011, 100, 101, 110, 111, 000...
Problem: carries ripple from bit 0 to bit n — outputs don't all change simultaneously
Causes glitches in some applications
Synchronous Counter
All flip-flops share the same clock. Logic determines when each bit toggles.
Q₀: toggle every cycle
Q₁: toggle when Q₀ = 1
Q₂: toggle when Q₁ = 1 AND Q₀ = 1
No ripple delay — all outputs change at same clock edge
Mod-N Counter
Counts 0 to N-1, then resets to 0.
Mod-6 counter: counts 0,1,2,3,4,5,0,1,2...
Implementation: when state reaches N, synchronously reset all flip-flops to 0
Finite State Machines (FSM)
Moore Machine
Output depends only on CURRENT STATE.
State → determines output
Input → determines next state
Diagram: states are circles labelled with (State/Output)
Transitions are arrows labelled with Input
Advantage: simpler, output is stable (not affected by input glitches)
Mealy Machine
Output depends on CURRENT STATE AND CURRENT INPUT.
State + Input → determines output AND next state
Diagram: states are circles, transitions labelled with "Input/Output"
Advantages:
- Fewer states needed (same behaviour with fewer states than Moore)
- Responds one clock cycle earlier (output changes with input, not waiting for next clock)
Example: 1011 sequence detector
Detect if the last 4 bits of input form "1011"
Mealy version: 4 states (S0, S1, S2, S3)
Moore version: 5 states (S0-S4, extra accepting state for output)
State Diagram → State Table → Circuit (Design Process)
Step 1: State diagram (draw circles for states, arrows for transitions)
Step 2: State table (present state + input → next state + output)
Step 3: State assignment (assign binary codes to each state)
Step 4: Flip-flop excitation (what J,K or D,T values are needed for each transition)
Step 5: K-map minimisation for excitation equations
Step 6: Draw the circuit!
Shift Registers
SISO: Serial In Serial Out — data shifts through chain of D flip-flops
SIPO: Serial In Parallel Out — shift register feeds parallel output after n clocks
PISO: Parallel In Serial Out — parallel load then shifts out serially
PIPO: Parallel In Parallel Out — just D flip-flops with direct load
Applications: serial communication, delay line, ring counter, Johnson counter
Quick Check
Q1. JK flip-flop: J=1, K=0, current Q=0. What is Q(t+1)? Answer: Q(t+1) = JQ' + K'Q = 1·1 + 1·0 = 1. Set operation.
Q2. Moore vs Mealy — which needs fewer states for the same behaviour? Answer: Mealy — because output is associated with transitions (not just states), so states that differ only in output can be merged.
Q3. A 4-bit ripple counter counts from 0 to 15. How many T flip-flops are needed? Answer: 4 flip-flops (one per bit). With T=1 always, they toggle: FF0 every cycle, FF1 every 2 cycles, FF2 every 4, FF3 every 8.
Key Formulas
- JK FF characteristic: Q(t+1) = JQ' + K'Q
- T FF characteristic: Q(t+1) = T⊕Q
- D FF characteristic: Q(t+1) = D
GATE Exam Tips
- ★SR forbidden state: S=R=1. JK resolves this: J=K=1 means toggle.
- ★Moore output changes only with state change; Mealy output changes immediately with input.
- ★Mealy responds one cycle earlier than Moore — this is a classic GATE question.
- ★For synthesis questions: use excitation tables to find FF inputs, then K-map to minimise.
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