Data acquisition systems and sampling

Why it matters

Every modern measurement or control loop ends in a number inside a microcontroller, PLC or PC. How often you sample and how many bits you convert with decide whether that number truly represents the physical signal. Under-sampling creates false frequencies (aliases) that no software can remove, and too few bits hide the small changes you were trying to see.

Key ideas

Chain of a data acquisition system (DAQ) Sensor → signal conditioning (bridge, amplifier, anti-aliasing filter) → multiplexer (if several channels share one converter) → sample-and-hold → analogue-to-digital converter (ADC) → processor, storage or controller. Output channels use a digital-to-analogue converter (DAC) and a driver.

Sampling

• Sampling takes the value of a continuous signal every T_s seconds; f_s = 1/T_s is the sampling rate.
• Nyquist–Shannon theorem: a band-limited signal whose highest frequency is f_max can be reconstructed exactly from its samples if f_s > 2·f_max. The quantity 2·f_max is the Nyquist rate; f_s/2 is the Nyquist (folding) frequency.
• Aliasing: any component above f_s/2 folds back and appears as a lower frequency |f − k·f_s| (k the integer that brings it into 0 to f_s/2). After sampling, an alias is indistinguishable from a real component.
• Anti-aliasing filter: an analogue low-pass filter placed before the ADC to remove content above f_s/2. Real filters are not brick walls, so practical systems sample at 5–10 times f_max (more for control loops, where sampling delay also costs phase margin).
• Sample-and-hold: holds the input constant while the ADC converts, so a changing signal does not corrupt the conversion.

Quantisation and resolution

• An n-bit ADC has 2ⁿ output codes. The step size (one LSB, quantisation step) is Q = V_FS/2ⁿ, where V_FS is the full-scale input range. Some textbooks write V_FS/(2ⁿ − 1), which is the step between the lowest and highest code values; for n ≥ 8 the two differ by less than 0.4 %. State which you use.
• Quantisation error: with rounding, the error lies within ±Q/2; it behaves like noise of RMS value Q/√12.
• Ideal signal-to-quantisation-noise ratio for a full-scale sine: SNR ≈ 6.02·n + 1.76 dB. Each extra bit adds about 6 dB.
• Resolution is not accuracy: offset, gain error, nonlinearity, noise and the reference voltage's tolerance all add to the error.

ADC types

• Successive approximation (SAR): one bit decided per clock, n clocks per conversion; the workhorse of microcontrollers (10–16 bit, up to a few MS/s).
• Flash: 2ⁿ − 1 comparators, fastest, low resolution, high power.
• Dual-slope (integrating): slow but rejects mains noise if the integration time is a multiple of 20 ms (50 Hz); used in digital multimeters.
• Sigma-delta: heavy oversampling plus digital filtering; high resolution (16–24 bit) for slow signals such as load cells and thermocouples.

Multiplexing When N channels share one ADC through a multiplexer, the ADC must run at N × (per-channel rate), and samples on different channels are taken at slightly different instants (skew), unless simultaneous sample-and-hold is used.

Formulas

f_s > 2·f_max — sampling theorem; f_s: sampling rate (Hz or samples/s), f_max: highest frequency present (Hz).

f_alias = |f − k·f_s| — apparent frequency (Hz) of a component f after sampling, with integer k chosen so that 0 ≤ f_alias ≤ f_s/2.

Q = V_FS / 2ⁿ — quantisation step (V); V_FS: full-scale range (V), n: number of bits.

e_q,max = ±Q/2 — maximum quantisation error with rounding (V).

SNR ≈ 6.02·n + 1.76 — ideal SNR (dB) for a full-scale sine.

D = round(V_in / Q) — output code (decimal) for an input V_in (V) on a unipolar ADC.

f_ADC = N·f_s,ch — required aggregate conversion rate for N multiplexed channels, each sampled at f_s,ch.

t_conv ≤ 1 / f_ADC — time available per conversion (s).

Worked examples

Example 1 (standard): resolution of a temperature channel Given: a temperature transmitter gives 0–10 V for 0–100 °C, read by a 12-bit unipolar ADC with a 0–10 V range. The highest frequency of interest is 1 Hz.

1. Quantisation step: Q = V_FS/2ⁿ = 10/4096 = 2.441×10⁻³ V = 2.44 mV.
2. Maximum quantisation error: ±Q/2 = ±1.22 mV.
3. Sensitivity: 10 V / 100 °C = 0.1 V/°C, so one step is 2.441×10⁻³/0.1 = 0.0244 °C.
4. Minimum sampling rate: f_s > 2·f_max = 2 Hz; practical choice 10–20 Hz with a low-pass filter around 2–5 Hz. Answer: Q ≈ 2.44 mV ≈ 0.024 °C per count; sample faster than 2 Hz (about 10 Hz in practice).

Example 2 (GATE level): aliasing, bits and multiplexing (a) A vibration signal contains components at 30 Hz and 70 Hz. It is sampled at 100 Hz without an anti-aliasing filter. What frequencies appear in the sampled data?

1. Nyquist frequency = f_s/2 = 50 Hz. The 30 Hz component is below it and appears correctly.
2. For 70 Hz: f_alias = |70 − 1 × 100| = 30 Hz. Answer: both components appear at 30 Hz, so the 70 Hz content is hidden inside the true 30 Hz reading and cannot be separated afterwards.

(b) The measurement must resolve 0.01 % of full scale. Minimum number of bits?

1. Need 2ⁿ ≥ 1/0.0001 = 10 000.
2. log₂(10 000) = 13.29, so n = 14 (2¹⁴ = 16 384). Answer: 14 bits (ideal SNR ≈ 6.02 × 14 + 1.76 = 86.0 dB).

(c) Eight such channels are multiplexed into one ADC, each to be sampled at 2 kS/s. Required ADC rate and maximum conversion time?

1. f_ADC = N·f_s,ch = 8 × 2000 = 16 000 S/s.
2. t_conv ≤ 1/f_ADC = 1/16 000 = 62.5 µs (including multiplexer settling). Answer: 16 kS/s; at most 62.5 µs per conversion.

Common mistakes

• Saying the sampling rate must be "at least" 2·f_max and then sampling a sine at exactly 2f: the samples can all land on zero crossings. The strict condition is f_s > 2·f_max.
• Believing that a digital filter after the ADC removes aliasing. The anti-aliasing filter must be analogue and come before sampling.
• Mixing up resolution (step size) with accuracy, or quoting resolution in bits when the question asks for volts.
• Forgetting that multiplexing divides the ADC rate among channels.
• Using 2ⁿ in one step and 2ⁿ − 1 in another; pick one and state it.
• Ignoring the signal's harmonics: a 50 Hz square wave has content at 150 Hz, 250 Hz and beyond.

For GATE ME

Typical items: minimum sampling rate, the alias frequency of an undersampled sinusoid, quantisation step and error for an n-bit ADC, the number of bits needed for a stated resolution, and the output code for a given input. Conceptual MCQs test the role of the anti-aliasing filter, sample-and-hold, and the differences between ADC types. Practise the folding calculation and powers of two until they are instant.

Quick check

1. What is the Nyquist rate for a signal whose highest frequency is 500 Hz?
2. A 900 Hz sine is sampled at 1 kHz. At what frequency does it appear?
3. What is the step size of a 10-bit ADC with a 0–5 V range (using 2ⁿ)?
4. How many dB of ideal SNR does each additional bit add?
5. Where must the anti-aliasing filter be placed?

Answers: 1. 1000 Hz. 2. 100 Hz. 3. 5/1024 ≈ 4.88 mV. 4. About 6 dB. 5. In the analogue path, before the sample-and-hold/ADC.