Memory and Programmable Logic Devices

Why it matters

Memory stores data and instructions; programmable logic implements Boolean and sequential hardware. Organization, timing and programming technology determine which device suits an application.

Memory types

SRAM stores bits in bistable cells and needs power but no periodic refresh. DRAM stores charge and requires refresh. Both common forms are volatile. ROM and flash retain data without power, although endurance and retention are finite. Random access describes addressing, not inherently volatility; nonvolatile RAM technologies also exist.

Programmable logic

A PLA has programmable AND and OR arrays. A traditional PAL has a programmable AND array and a fixed OR array. An FPGA contains configurable logic resources, registers and routing, often with embedded memory and other hard blocks. Its configuration may be volatile or nonvolatile depending on technology.

Capacity and timing

A memory organized as 2^A words of W bits needs A address bits and has 2^A W storage bits. Byte capacity is total bits divided by eight.

Read access time is the delay from the specified address/control event until valid read data. Write pulse width, setup/hold times and cycle time are separate specifications. Access time is not generally read time plus write time. Add durations only when a question explicitly asks for consecutive operations with no overlap and states their overhead.

Worked example

A 4K × 8 memory contains 4096 words, each eight bits wide. It needs log2(4096) = 12 address lines and eight data lines. Capacity is 32768 bits = 4096 bytes = 4 KiB.

To build 8K × 16 from 4K × 8 chips, use two chips in parallel for 16-bit word width and two such banks for 8K depth: four chips total. The high address bit selects the bank and the lower 12 address bits select a word within it. Output-enable/chip-select logic must prevent bus contention.

If a device separately specifies 10 ns read access and 15 ns write-operation duration, these do not define a single 25 ns access time. Only an explicitly sequential read-then-write exercise with no additional overhead would total 25 ns.

Common mistakes

Confusing bits with bytes, memory depth with width, address lines with data lines, or read access with cycle time; treating flash as infinitely rewritable; and confusing fixed versus programmable arrays in PAL and PLA.

Quick check

1. How many addresses can 10 address bits select?
2. Which common RAM needs refresh?
3. Which arrays are programmable in a PLA?

Answers: 1. 1024. 2. DRAM. 3. Both AND and OR arrays.