Phase Locked Loops (PLLs)

Why it matters

A phase-locked loop synchronizes an oscillator to a reference and supports frequency synthesis, clock recovery and demodulation. A phase detector, loop filter, VCO and feedback path form the loop.

Key ideas

The phase detector compares reference and feedback phase. Near its linear operating point, v_d = K_d φ_e, with K_d in V/rad. The loop filter shapes acquisition, stability and noise transfer; it does more than simply remove ripple. A VCO follows f_out = f_free + K_f v_c, with K_f in Hz/V. If gain is specified in rad/s/V, divide by 2π to obtain Hz/V.

At steady lock in a direct-feedback PLL, reference and output frequencies are equal, although phase error may be nonzero. With a divide-by-N feedback counter, f_out/N = f_ref, so f_out = N f_ref. A persistent frequency difference would cause phase error to grow, contradicting steady lock.

Lock/hold range describes maintaining lock; capture/acquisition range describes acquiring it from an unlocked condition. Exact ranges depend on loop architecture, filter and detector.

Worked example

A direct-feedback PLL has f_ref = 10 MHz, VCO free-running frequency 9.95 MHz, K_f = 1 MHz/V, and a linear phase detector K_d = 0.5 V/rad. Assume the loop is stably locked, the loop filter has unity DC gain, and all ranges permit this point.

The VCO must shift by 10 − 9.95 = 0.05 MHz. Thus v_c = 0.05 MHz/(1 MHz/V) = 0.05 V. Since v_c = K_d φ_e in this example, φ_e = 0.05/0.5 = 0.1 rad. The locked output is 10 MHz, not 10.05 MHz. The shift is measured from the free-running frequency, not from the reference.

For a separate synthesizer with N = 20 and f_ref = 1 MHz, steady lock gives f_out = 20 MHz.

Small-signal phase model

For direct feedback, VCO phase gain is K_v/s with K_v in rad/s/V. If the filter is F(s), phase closed-loop transfer is K_d K_v F(s)/(s + K_d K_v F(s)). This linearization applies near lock and does not predict every nonlinear capture behavior.

Common mistakes

Adding a correction to the reference instead of the free-running frequency; mixing hertz and radians per second; ignoring dividers; assuming capture and hold ranges are identical.

Quick check

1. Can a directly fed-back PLL stay locked with a constant nonzero frequency difference?
2. What does a divide-by-10 loop produce from a 2 MHz reference in lock?
3. What controls the VCO frequency?

Answers: 1. No. 2. 20 MHz. 3. Its control voltage, according to the VCO tuning characteristic.