Sampled Data Systems

Sampling and holding

A sampled-data loop contains both continuous dynamics and sampled signals. A sampler records values every T seconds; a zero-order hold maintains each command until the next update. A discrete transfer model depends on the sampling period and hold assumption. Sampling frequency is fs = 1/T. For an ideally bandlimited input, sampling must exceed twice its highest frequency for unique reconstruction; practical anti-alias filtering and control bandwidth require margin. The reconstruction criterion alone does not guarantee a satisfactory control loop.

Exact state update

For xdot = Ax + Bu with input held constant over each interval: x[k+1] = Ad x[k] + Bd u[k], where Ad = exp(AT) and Bd = ∫0ᵀ exp(Aτ)B dτ. Continuous modes map as z = exp(sT). Left-half-plane poles map inside the unit circle. A causal rational discrete system is BIBO stable when every uncancelled pole has |z| < 1.

Worked example

For ydot = −y + u and T = 0.1 s, Ad = exp(−0.1) = 0.904837 and Bd = 1 − exp(−0.1) = 0.095163. y[k+1] = 0.904837y[k] + 0.095163u[k]. With zero initial state, G(z) = 0.095163/(z − 0.904837), equivalently 0.095163z⁻¹/(1 − 0.904837z⁻¹). For a unit step y[k] = 1 − 0.904837^k. At k = 10, time is 1 s and y = 0.63212.

Common mistakes

Do not equate s with z. Do not omit sample delay or the hold assumption. Stable continuous dynamics do not guarantee stability after arbitrary digital feedback gains and computational delays are introduced.

Quick check

1. What does a zero-order hold do? Keeps the command constant between updates.
2. Where must stable discrete poles lie? Strictly inside the unit circle.
3. Is the sample period part of the model? Yes.